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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2006, zarlink semiconductor inc. all rights reserved. features ? 2048 channel x 2048 channel non-blocking digital time division multiplex (tdm) switch at 8.192 and 16.384 mbps or using a combination of ports running at 2.048, 4.096, 8.192 and/or 16.384 mbps ? 32 serial tdm input, 32 serial tdm output streams ? integrated digital phase-locked loop (dpll) exceeds telcordia gr-1244-core stratum 3 specifications ? output clocks have less than 1 ns of jitter (except for the 1.544 mhz output) ? dpll provides holdover, freerun and jitter attenuation features with four independent reference source inputs ? programmable key dpll parameters (filter corner frequency, locking range, auto-holdover hysteresis range, phase slope, lock detector range) ? exceptional input clock c ycle to cycle variation tolerance (20 ns for all rates) ? output streams can be configured as bi- directional for connection to backplanes november 2006 ordering information zl50018gac 256 ball pbga trays zl50018qcc 256 lead lqfp trays zl50018qcg1 256 lead lqfp* trays, bake & drypack zl50018gag2 256 ball pbga** trays, bake & drypack *pb free matte tin **pb free tin/silver/copper -40 c to +85 c zl50018 2 k digital switch with enhanced stratum 3 dpll data sheet figure 1 - zl50018 functional block diagram data memory internal registers & microprocessor interface output hiz te s t p o r t control osc dpll s/p converter stohz[15:0] fpo[3:0] cko[5:0] stio[31:0] ref0 osci osco connection memory mot_intel ds _rd cs d[15:0] a[13:0] tms tdi tdo tck trst output timing sti[31:0] ref1 ref2 ref3 fpo_off[2:0] ref_fail0 ref_fail1 ref_fail2 ref_fail3 irq p/s converter dta _rdy r/w _wr osc_en input timing fpi cki mode_4m0 mode_4m1 ode reset v ss v dd_io v dd_core v dd_ioa v dd_corea zarlink semiconductor us patent no. 5,602,884, uk patent no. 0772912, france brevete s.g.d.g. 0772912; germany dbp no. 69502724.7-08
zl50018 data sheet 2 zarlink semiconductor inc. ? per-stream input and output data rate conversion sele ction at 2.048, 4.096, 8.192 or 16.384 mbps. input and output data rates can differ ? per-stream high impedance control outputs (stohz) for up to 16 output streams ? per-stream input bit delay with flexible sampling point selection ? per-stream output bit and fractional bit advancement ? per-channel itu-t g.711 pcm a-law/ -law translation ? multiple frame pulse and reference clock output ? input clock: 4.096 mhz, 8.192 mhz, 16.384 mhz ? input frame pulses: 61 ns, 122 ns, 244 ns ? per-channel constant or variable throughput delay for frame integrity and low latency applications ? per stream bit error rate test circuits ? per-channel high impedance output control ? per-channel message mode ? control interface compatible with intel and motorola 16-bit non-multiplexed buses ? connection memory block programming ? supports st-bus and gci-bus standards for input and output timing ? ieee-1149.1 (jtag) test port ? 3.3 v i/o with 5 v tolerant inputs; 1.8 v core voltage applications ? pbx and ip-pbx ? small and medium digital switching platforms ? wireless base stations and controllers ? remote access servers and concentrators ? multi service access platforms ? digital loop carriers ? computer telephony integration
zl50018 data sheet 3 zarlink semiconductor inc. description the zl50018 is a maximum 2,048 x 2,048 channel non-blocking digital time division multiplex (tdm) switch. it has thirty-two input streams (sti0 - 31) and thirty-two output streams (stio0 - 31). the device can switch 64 kbps and nx64 kbps tdm channels from any input stream to any output stream. each of the input and output streams can be independently programmed to operate at any of the followi ng data rates: 2.048, 4.096, 8.192 or 16.384 mbps. the zl50018 provides up to sixteen high impedance control outputs (stohz0 - 15) to support the use of external tristate drivers for the first sixteen output streams (s tio0 - 15). the output streams can be configured to operate in bi-directional mode, in which ca se sti0 - 31 will be ignored. the device contains two types of internal memory - dat a memory and connection memory. there are four modes of operation - connection mode, message mode, ber mode a nd high impedance mode. in connection mode, the contents of the connection memory define, for each ou tput stream and channel, the source stream and channel (the actual data to be output is stored in the data memory ). in message mode, the connection memory is used for the storage of microprocessor data. using zarlink' s message mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. this feature is useful for transferring control and status information for external circuits or other tdm devices. in ber mode the output channel data is replaced with a pseudorandom bit sequence (prbs) from one of 32 prbs generators that generates a 2 15 -1 pattern. on the input side channels can be routed to one of 32 bit error detectors. in high impedance mode the selected output channel can be put into a high impedance state. when the device is operating as a timing master, the inte rnal digital pll is in use. in this mode, an external 20.000 mhz crystal is required for the on-chip crystal osci llator. the dpll is phase-locked to one of four input reference signals (which can be 8 khz, 1.544, 2.048, 4.096 , 8.192, 16.384 or 19.44 mhz provided on ref0 - 3). the on-chip dpll operates in normal, holdover or freerun mode and offers ji tter attenuation. the jitter attenuation function exceeds the stratum 3 specification. the configurable non-multiplexed micr oprocessor port allows users to program various device operating modes and switching configurations. users ca n employ the microprocessor port to pe rform register read/ write, connection memory read/write, and data memory r ead operations. the port is configurable to interface with either motorola or intel-type microprocessors. the device also supports the mandatory requirements of the ieee-1149.1 (jtag) st andard via the test port.
zl50018 data sheet table of contents 4 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.0 pinout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 bga pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 qfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.0 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 data rates and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 external high impedance control, stohz0 - 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 input clock (cki) and input frame pulse (fpi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0 st-bus and gci-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.0 output timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.0 data input delay and data output advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 input bit delay programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 input bit sampling point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 output advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 fractional output bit advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 external high impedance control advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 constant delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.0 connection memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.0 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 memory block programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.0 device operation in master mode and slave modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 master mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.2 divided slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.3 multiplied slave mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.0 overall operation of the dpll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.1 dpll timing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.2 holdover mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.3 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.3.1 automatic reference switching wi thout preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1.3.2 automatic reference switching with preference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.1.4 freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1.5 software controlled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1.6 dpll internal reset mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.0 dpll frequency behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.1 input frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.2 input frequencies selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.3 output frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13.4 pull-in/hold-in range (also called locking range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.0 jitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.1 input clock cycle to cycle timing variation tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.2 input jitter acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.3 jitter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.0 dpll specific functions and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
zl50018 data sheet table of contents 5 zarlink semiconductor inc. 15.1 lock detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.2 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.3 phase alignment speed (phase slope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15.4 fast locking mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.5 reference monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.6 single period reference monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15.7 multiple period reference monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.0 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 17.2 device initialization on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 17.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 18.0 pseudo-random bit generation and error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 19.0 pcm a-law/m-law translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 20.0 quadrant frame programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.0 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21.3 test data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 21.4 bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 22.0 register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 23.0 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 24.0 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 24.1 memory address mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 24.2 connection memory low (cm_l) bit assi gnment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 24.3 connection memory high (cm_h) bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 25.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25.1 osci master clock requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25.1.1 external crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25.1.2 external clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 26.0 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27.0 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
zl50018 data sheet list of figures 6 zarlink semiconductor inc. figure 1 - zl50018 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - zl50018 256-ball 17 mm x 17 mm pbga (as viewed through top of package) . . . . . . . . . . . . . . . . . . 11 figure 3 - zl50018 256-lead 28 mm x 28 mm lqfp (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 - input timing when ckin1 - 0 bits = ?10? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 5 - input timing when ckin1 - 0 bits = ?01? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6 - input timing when ckin1 - 0 = ?00? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7 - output timing for cko0 and fpo0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8 - output timing for cko1 and fpo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9 - output timing for cko2 and fpo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10 - output timing for cko3 and fpo3 with ckofpo3sel1-0= ?11? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 11 - output timing for cko4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12 - output timing for cko5 and fpo5 (fpo_off2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13 - input bit delay timing diagram (st-bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14 - input bit sampling point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15 - input bit delay and factional sampling point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16 - output bit advancement timing diagram (st-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17 - output fractional bit advancement timing diagram (st-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18 - channel switching external high impedance control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19 - data throughput delay for variable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20 - data throughput delay for constant delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 21 - automatic reference switching state diagram with no preferred reference . . . . . . . . . . . . . . . . . . 40 figure 22 - automatic reference switching state diagrams with preferred reference . . . . . . . . . . . . . . . . . . . . 41 figure 23 - crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 24 - clock oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 25 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 26 - motorola non-multiplexed bus timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 27 - motorola non-multiplexed bus timing - write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 28 - intel non-multiplexed bus timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 29 - intel non-multiplexed bus timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 30 - jtag test port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 31 - frame pulse input and clock input timing diagram (st-bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 32 - frame pulse input and clock input timing diagram (gci-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 33 - st-bus input timing diagram when operated at 2 mbps, 4 mbps, 8 mbps. . . . . . . . . . . . . . . . . . . 115 figure 34 - st-bus input timing diagram when operated at 16 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16 figure 35 - gci-bus input timing diagra m when operated at 2 mbps, 4 mbps, 8 mbps . . . . . . . . . . . . . . . . . . 116 figure 36 - gci-bus input timing diagram when operated at 16 mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 17 figure 37 - st-bus output timing diagram when operated at 2, 4, 8 or 16 mbps . . . . . . . . . . . . . . . . . . . . . . 119 figure 38 - gci-bus output timing diagra m when operated at 2, 4, 8 or 16 mbps . . . . . . . . . . . . . . . . . . . . . . 119 figure 39 - serial output and external control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 40 - output drive enable (ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 41 - input and output frame boundary offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 42 - fpo0 and cko0 or fpo3 and cko3 (4.096 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 43 - fpo1 and cko1 or fpo3 and cko3 (8.192 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 44 - fpo2 and cko2 or fpo3 and cko3 (16.384 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 45 - fpo3 and cko3 (32.768 mhz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 46 - fpo4 and cko4 timing diagram (1.544/2.048 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 47 - cko5 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 48 - ref0 - 3 reference input/output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
zl50018 data sheet list of figures 7 zarlink semiconductor inc. figure 49 - output timing (st-bus format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
zl50018 data sheet list of tables 8 zarlink semiconductor inc. table 1 - cki and fpi configurations for master and divided slav e modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2 - cki and fpi configurations for multiplied slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3 - output timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4 - delay for variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5 - connection memory low after block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 6 - connection memory high after block programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 7 - zl50018 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8 - preferred reference selection options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9 - dpll input reference frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 10 - generated output frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11 - values for single period limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 12 - default values for single period limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13 - default multi-period hysteresis limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14 - input and output voice and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 15 - definition of the four quadrant frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 16 - quadrant frame bit replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 17 - address map for registers (a13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 18 - control register (cr) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19 - internal mode selection register (ims) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 20 - software reset register (srr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 21 - output clock and frame pulse cont rol register (ocfcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 22 - output clock and frame pulse sele ction register (ocfsr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23 - fpo_off[n] register (fpo_off[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24 - internal flag register (ifr) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 25 - ber error flag register 0 (berfr0) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 26 - ber error flag register 1 (berfr1) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 27 - ber receiver lock register 0 (berlr0) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 28 - ber receiver lock register 1 (berlr1) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 29 - dpll control register (dpllcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 30 - reference frequency register (rfr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 31 - centre frequency register - lower 16 bits (cfrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 32 - centre frequency register - upper 10 bits (cfru). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 33 - software delta frequency register (swdfr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 34 - frequency offset register (for) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 35 - frequency locking range register (flrr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 36 - lock detector threshold register (ldtr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 37 - lock detector interval register (ldir) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 38 - slew rate limit register (srlr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 39 - bandwidth control register (bwcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 40 - reference change control register (rccr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 41 - reference change status register (rcsr) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 42 - multi-period near upper limit regi ster - lower 16 bits (mpnulrl) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 43 - multi-period near upper limit r egister - upper 16 bits (mpnulru). . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 44 - multi-period far upper limit regi ster - lower 16 bits (mpfulrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 45 - multi-period far upper limit regi ster - upper 16 bits (mpfulru) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 46 - multi-period near lower limit register - lower 16 bits (mpnllrl) . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 47 - multi-period near lower limit register - upper 16 bits (mpnllru) . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 48 - multi-period far lower limit regist er - lower 16 bits (mpfllrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
zl50018 data sheet list of tables 9 zarlink semiconductor inc. table 49 - multi-period far lower limit regi ster - upper 16 bits (mpfllru) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 50 - multi-period count register - lower 16 bits (rnmpcrl) bits, (n = 0 - 3) . . . . . . . . . . . . . . . . . . . . . . 82 table 51 - multi-period count register - uppe r 16 bits (rnmpcru) bits, (n = 0 - 3) . . . . . . . . . . . . . . . . . . . . . . 83 table 52 - upper limit register (rnulr) bits, (n = 0 - 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 53 - lower limit register (rnllr) bits, (n = 0 - 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 54 - interrupt register (ir) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55 - interrupt mask register (imr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56 - interrupt clear register (icr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 57 - reference failure status register (rsr) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 58 - reference mask register (rmr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 59 - reference frequency status register (rfsr) bits - read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 60 - output jitter control register (ojcr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 61 - stream input control register 0 - 31 (sicr0 - 31) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62 - stream input quadrant frame regi ster 0 - 31 (siqfr0 - 31) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 63 - stream output control register 0 - 31 (socr0 - 31) bi ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 64 - ber receiver start register [n] (brsr[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 65 - ber receiver length register [n] (brlr[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 66 - ber receiver control register [n] (brcr[n]) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 67 - ber receiver error register [n] (brer[n]) bits - read only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 68 - address map for memory locations (a13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 69 - connection memory low (cm_l) bit assignment when cmm = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 70 - connection memory low (cm_l) bit assignment when cmm = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 71 - connection memory high (cm_h) bit assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
zl50018 data sheet 10 zarlink semiconductor inc. changes summary the following table captures the changes from january 2006 to november 2006. the following table captures the changes from the october 2004 issue. page item change 1 updated ordering information. page item change 39, 76, 77 section 12.1, ?dpll timing modes? on page 39 rccr register bits ?fdm1 - 0? on page 76 rcsr register bits ?dpm1 - 0? on page 77 ? the on-chip dpll?s normal, holdover, automatic, and freerun modes are now collectively referred to as dpll timing mode s instead of operation modes. this change is to avoid confusion with the two main device operating modes; the master and slave modes. 39, 40 section 12.1.3.1, ?automatic reference switching without preferences? on page 39 and section 12.1.3.2, ?automatic reference switching with preference? on page 40 ? section 12.1.3.1 and sect ion 12.1.3.2 added to clarify the dpll?s automatic reference switching with and without preference operations in automatic timing mode. 42, 45 section 12.1.4, ?freerun mode? on page 42, and section 15.4, ?fast locking mode? on page 45 ? added description to specify that the device should not be in freerun and fast lock modes simultaneously. this is important in order to avoid incorrect output frame pulse generation. 72 table 36, lock detector threshold register (ldtr) bits ? clarified threshold calculations. 74 table 39, ?bandwidth control register (bwcr) bits? note 3. ? added a table footnote to specify that the dpll?s fastlock and freerun modes should not be set simultaneously. 75 table 40, ?reference change control register (rccr) bits? bits ?prs1 - 0? and bits ?pms2 - 0? ? added description to clarify that only two consecutive references can be used in automatic timing mode with a preferred reference. 76 table 40, ?reference change control register (rccr) bits?, bits ?fdm1 - 0? ? added description to specify the device should not be in freerun and fast lock modes simultaneously.
zl50018 data sheet 11 zarlink semiconductor inc. 1.0 pinout diagrams 1.1 bga pinout figure 2 - zl50018 256-ball 17 mm x 17 mm pbga (as viewed through top of pa ckage) 12345678 910111213141516 a v ss sti29 sti28 sti27 sti25 sti26 sti24 nc nc stio22 stio23 stio21 stio20 nc nc v ss a b sti31 sti10 sti5 sti4 cko2 sti0 cko0 ref2 v dd_ corea fpi cki ic_ open ic_ open osci ode stio19 b c sti30 sti9 v ss sti7 sti6 sti1 cko1 ref_ fail2 v ss ic_ open ic_ open osco ic_gnd v ss stio15 stio18 c d sti17 sti11 v dd_io sti3 sti2 cko4 ref3 ref1 ref_ fail0 v ss fpo_ off1 osc_ en stio13 v dd_io stio14 stio16 d e sti16 sti14 sti8 v dd_io v ss v dd_ core ref_ fail3 ref_ fail1 ref0 nc v dd_ core v ss v dd_io stio12 fpo2 stio17 e f sti19 sti15 sti12 sti13 v dd_io v dd_ core v dd_ core v ss v ss v dd_ core v dd_ core v dd_io ic_ open fpo3 fpo_ off2 stohz15 f g sti18 reset ic_gnd ic_ open tdo v dd_io v ss v ss v ss v ss v dd_io a12 a13 fpo1 fpo0 stohz14 g h sti21 v ss v ss v dd_ corea cko5 v ss v ss v ss v ss v ss a7 a9 a10 fpo_ off0 a11 stohz12 h j sti20 v dd_ioa v dd_ioa v ss v ss cko3 v ss v ss v ss v ss a3 a4 a5 a8 a6 stohz13 j k sti22 v ss tms v ss v dd_ corea v dd_io v ss v ss v ss v ss v dd_io ic_ open a0 a2 a1 stohz11 k l sti23 v dd_ corea trst tck v dd_io v dd_ core v dd_ core v ss v ss v dd_ core v dd_ core v dd_io stio10 stio11 stio9 stohz10 l m stio25 nc tdi d0 v ss v dd_ core v dd_ core d6 d10 v dd_ core v dd_ core v ss mot _intel mode_ 4m0 stio8 stohz9 m n stio24 nc v dd_io stio0 stohz3 d1 d5 d7 d11 d13 r/w _wr dta _ rdy stio4 v dd_io stohz5 stohz8 n p stio26 nc v ss stio1 stio3 stohz1 d3 d8 d14 irq stio5 stohz4 stohz6 v ss stohz7 nc p r stio27 nc stohz0 stio2 stohz2 d2 d4 d9 d12 d15 cs ds _rd mode_ 4m1 stio6 stio7 nc r t v ss stio28 stio29 stio31 stio30 nc nc nc nc nc nc nc nc nc nc v ss t 12345678 910111213141516 note: a1 corner identified by metallized marking. note: pinout is shown as viewed through top of package.
zl50018 data sheet 12 zarlink semiconductor inc. 1.2 qfp pinout figure 3 - zl50018 256-lead 28 mm x 28 mm lqfp (top view) 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 22 24 26 28 30 20 18 16 14 12 10 8 6 4 2 120 102 104 106 108 110 114 116 118 112 52 54 56 58 60 50 48 46 44 42 40 38 36 34 32 100 82 84 86 88 90 94 96 98 92 80 66 68 70 74 76 78 72 132 134 136 138 140 142 144 146 148 150 cki fpi ic_open ic_open ic_open ic_open osco osci vdd_io vss ic_gnd ode vdd_io stio_23 stio_22 stio_21 stio_20 62 64 122 124 126 128 182 184 186 188 190 sti25 sti24 vss vdd_io sti_7 sti_6 sti_3 sti_2 sti_1 sti_0 cko4 vss ref_fail2 ref2 ref_fail1 ref1 ref_fail0 ref0 vss sti27 sti26 sti_5 sti_4 vdd_io cko2 cko1 vss vdd_core cko0 vss vdd_io ref_fail3 ref3 vss vdd_corea sti_22 vdd_io sti_23 sti_21 sti_20 sti_19 sti_18 sti_17 vdd_io trst tck tms vss vdd_core vss vdd_corea vss vss cko3 vdd_ioa vdd_corea vss vss cko5 vdd_ioa vss vdd_corea vss vss vdd_core tdo reset ic_open ic_gnd vss vdd_io sti_15 sti_14 sti_11 sti_10 sti_9 sti_8 sti30 sti31 sti_16 vss tdi sti29 vdd_io sti28 202 220 218 216 214 212 208 206 204 210 222 240 238 236 234 232 228 226 224 230 242 256 254 252 248 246 244 250 200 198 196 194 vss sti_13 sti_12 stio_28 stio_29 stio_30 stio_31 vdd_io vss stio_0 stio_1 stio_2 stio_3 stohz_0 stohz_1 stohz_2 stohz_3 vdd_io vss d0 vdd_core vss d1 d2 d3 d4 d5 d7 d8 d9 d6 vdd_io vss d10 vdd_core vss d11 d12 d13 d14 d15 r/w _wr cs mot_intel ds _rd irq dta _rdy mode_4m0 vdd_core vss mode_4m1 vdd_io vss stio_4 stio_5 stio_6 stio_7 stohz_4 stohz_5 stohz_6 stohz_7 vdd_io vss nc nc nc nc nc vdd_io vss stio_8 stio_9 stio_10 stio_11 stohz_8 stohz_9 stohz_10 stohz_11 vdd_io ic_open vss vdd_core vss a0 a1 a2 a3 a4 a7 a6 a5 a11 a10 a9 a8 vdd_core vss a13 a12 ic_open vdd_io vss fpo_off0 fpo0 fpo_off1 fpo1 fpo2 fpo_off2 fpo3 vdd_core vss osc_en vdd_io vss stio_12 stio_13 stio_14 stio_15 stohz_12 stohz_13 stohz_14 stohz_15 vdd_io vss stio_16 stio_17 stio_18 stio_19 nc nc nc nc nc nc nc vss vdd_core vss vss vdd_io stio_27 stio_24 stio_25 stio_26 vss nc nc nc 192 130 nc nc nc nc nc nc
zl50018 data sheet 13 zarlink semiconductor inc. 2.0 pin description pbga pin number lqfp pin number pin name description e6, e11, f6, f7, f10, f11, l6, l7, l10, l11, m6, m7, m10, m11 19, 33, 45, 83, 95, 109, 146, 173, 213, 233 v dd_core power supply for the core logic: +1.8 v h4, k5, b9, l2 217, 231, 157, 224 v dd_corea power supply for analog circuitry: +1.8v d3, d14, e4, e13, f5, f12, g6, g11, k6, k11, l5, l12, n3, n14 5, 15, 29, 49, 57, 69, 79, 101, 113, 121, 133, 143, 160, 169, 177, 186, 195, 207, 241, 249 v dd_io power supply for i/o: +3.3 v j2, j3 220, 226 v dd_ioa power supply for the cko5 and cko3 outputs: +3.3 v a1, a16, c3, c9, c14, d10, e5, e12, f8, f9, g7, g8, g9, g10, h2, h3, h6, h7, h8, h9, h10, j4, j5, j7, j8, j9, j10, k2, k4, k7, k8, k9, k10, l8, l9, m5, m12, p3, p14, t1, t16 8, 17, 21, 31, 35, 47, 50, 60, 71, 81, 85, 97, 103, 111, 114, 123, 142, 145, 147, 156, 158, 162, 171, 175, 178, 188, 199, 209, 214, 216, 218, 222, 223, 228, 230, 232, 235, 242, 251 v ss ground
zl50018 data sheet 14 zarlink semiconductor inc. k3 234 tms test mode select (5 v-tolerant input with internal pull-up) jtag signal that controls the stat e transitions of the tap controller. this pin is pulled high by an internal pull-up resistor when it is not driven. l4 238 tck test clock (5 v-tolerant schmitt- triggered input with internal pull-up) provides the clock to the jtag test logic. l3 239 trst test reset (5 v-tolerant input with internal pull-up) asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low during power-up to ensure that the devi ce is in the normal functional mode. when jtag is not being used, this pin should be pulled low during normal operation. m3 240 tdi test serial data in (5 v-tolerant input with internal pull-up) jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up resistor when it is not driven. g5 212 tdo test serial data out (5 v- tolerant three-state output) jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag is not enabled. b12, b13, c10, c11, f13, g4, k12 80, 105, 150, 151, 152, 153, 210 ic_open internal test mode (5 v-tolerant input with internal pull-down) these pins may be left unconnected. c13, g3 144, 208 ic_gnd internal test mode enable (5 v-tolerant input): these pins must be low. a8, a9, a14, a15, e10, m2, n2, p2, p16, r2, r16, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15 61, 62, 63, 64, 65, 66, 67, 68, 134, 135, 136, 137, 138, 139, 140, 215, 219, 225, 229, 236, 237 nc no connect these pins must be left unconnected. m14, r13 46, 48 mode_4m0, mode_4m1 4 m input clock mode 0 to 1 (5 v-tolerant input with internal pull-down) these two pins should be tied together and are typically used to select cki = 4.096 mhz operation. see table 7, ?zl50018 operating modes? on page 37 for a detailed explanation. see table 18, ?control register (cr) bits? on page 55 for cki and fpi selection using the ckin1 - 0 bits. pbga pin number lqfp pin number pin name description
zl50018 data sheet 15 zarlink semiconductor inc. d12 107 osc_en oscillator enable (5 v-tolerant input with internal pull-down) if tied high, this pin indicates that there is a 20 mhz external oscillator interfacing with the device. if tied low, there is no oscillator and cki will be used for master clock generation. if the dpll is activated, an exter nal oscillator is required and this pin must be tied high. c12 149 osco oscillator clock out put (3.3 v output) if osc_en = ?1?, this pin should be connected to a 20 mhz crystal (see figure 23 on page 104) or left unconnected if a clock oscillator is connected to osci pin under normal operation (see figure 24 on page 105). if osc_en = 0, this pin must be left unconnected. b14 148 osci oscillator clock input (3.3 v input) if osc_en = ?1?, this pin should be connected to a 20 mhz crystal (see figure 23 on page 104) or to a clock oscillator under normal operation (see figure 24 on page 105). if osc_en = 0, this pin must be driven high or low by connecting either to v dd_io or to ground. e9, d8, b8, d7 161, 164, 166, 168 ref0 - 3 dpll reference inputs 0 to 3 (5 v-tolerant schmitt-triggered inputs) if the device is in master mode, these input pins accept 8 khz, 1.544 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz or 19.44 mhz timing references independently. one of these inputs is defined as the preferred or forc ed input reference for the dpll. the reference change control register (rccr) selects the control of the pr eferred reference. these pins are ignored if the device is in slave mode unless slv_dpllen (bit 13) in the control register (cr) is set. when these input pins are not in use, they must be driven high or low by connecting either to v dd_io or to ground. d9, e8, c8, e7 159, 163, 165, 167 ref_fail0 - 3 failure indication for dpll references 0 to 3 (5 v-tolerant three-state outputs) these output pins are used to indi cate input reference failure when the device is in master mode. if ref0 fails, ref_fail0 will be driven high. if ref1 fails, ref_fail1 will be driven high. if ref2 fails, ref_fail2 will be driven high. if ref3 fails, ref_fail3 will be driven high. if the device is in slave mode, these pins are driven low, unless slv_dpllen (bit 13) in the control register (cr) is set. pbga pin number lqfp pin number pin name description
zl50018 data sheet 16 zarlink semiconductor inc. g15, g14, e15, f14 102, 106, 110, 112 fpo0 - 3 st-bus/gci-bus frame pulse outputs 0 to 3 (5 v-tolerant three-state outputs) fpo0: 8 khz frame pulse corres ponding to the 4.096 mhz output clock of cko0. fpo1: 8 khz frame pulse corres ponding to the 8.192 mhz output clock of cko1. fpo2: 8khz frame pulse corresponding to 16.384 mhz output clock of cko2. fpo3: programmable 8khz frame pulse corresponding to 4.096, 8.192, 16.384, or 32.768 mhz output clock of cko3. in divided slave modes, the frame pulse width of fpo0 - 3 cannot be narrower than the input frame pulse (fpi) width. h14, d11 100, 104 fpo_off0 - 1 generated offset frame pulse outputs 0 to 1 (5 v-tolerant three-state outputs) individually programmable 8 khz frame pulses, offset from the output frame boundary by a programmable number of channels. f15 108 fpo_off2 or fpo5 generated offset frame pulse output 2 or 19.44 mhz frame pulse output (5 v-tolerant three-state output) as fpo_off2, this is an individually programmable 8 khz width frame pulse, offset from t he output frame boundary by a programmable number of channels. by programming the fp19en (bit 10) of fpoff2 register to high, this signal becomes fpo5, a non-offset frame pulse corresponding to the 19.44 mhz clock presented on cko5. fpo5 is only available in master mode or when the slv_dpllen bit in the control register is set high while the devi ce is in one of the slave modes. b7, c7, b5, j6, d6, h5 170, 172, 174, 227, 176, 221 cko0 - 5 st-bus/gci-bus clock outputs 0 to 5 (5 v-tolerant three-state outputs) cko0: 4.096 mhz output clock. cko1: 8.192 mhz output clock. cko2: 16.384 mhz output clock. cko3: 4.096, 8.192, 16.384 or 32. 768 mhz programmable output clock; cko4: 1.544 or 2.048 mhz programmable output clock. cko5: 19.44 mhz output clock. see section 6.0 on page 24 for details. in divided slave mode, the frequency of cko0 - 3 cannot be hi gher than input clock (cki). cko4 and cko5 are only availabl e in master mode or when the slv_dpllen bit in the control register is set high while the device is in one of the slave modes. pbga pin number lqfp pin number pin name description
zl50018 data sheet 17 zarlink semiconductor inc. b10 155 fpi st-bus/gci-bus frame pulse input (5 v-tolerant schmitt-triggered input) this pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. the frame pulse frequency is 8 khz. the frame pulse associated with the highest input or output data rate must be applied to this pi n when the device is operating in divided slave mode or master mode. the exception is if the device is operating in master mode with loopback (i.e., cki_lp is set in the control register). in that case, this input must be tied high or low externally. when the device is operating in multiplied slave mode, the frame pulse associated with the highest input data rate must be applied to this pin. for all modes (except master mode with loopback), if the data rate is 16.384 mbps, a 61 ns wide frame pulse must be used. by default, the device accepts a negative frame pulse in st-bus format, but it can accept a posi tive frame pulse instead if the fpinp bit is set high in the control register (cr). it can accept a gci-formatted frame pulse by programming the fpinpos bit in the control register (cr) to high. b11 154 cki st-bus/gci-bus clock input (5 v-tolerant schmitt triggered input) this pin accepts a 4.096, 8.192 or 16.384 mhz clock. the clock frequency associated with twice the highest input or output data rate must be applied to this pin when the device is operating in either divided slave mode or master mode. the exception is if the device is operating in master mode with loopback (i.e., cki_lp is set in th e control register). in that case, this input must be tied high or low externally. the clock frequency associated with twice the highest input data rate must be applied to this pin when the device is operating in multiplied slave mode. in all modes of operation (except master mode with loopback), when data is running at 16.384 mbps , a 16.384 mhz clock must be used. by default, the clock falli ng edge defines the input frame boundary, but the device allows t he clock rising edge to define the frame boundary by programming the ckinp bit in the control register (cr). pbga pin number lqfp pin number pin name description
zl50018 data sheet 18 zarlink semiconductor inc. b6, c6, d5, d4, b4, b3, c5, c4, e3, c2, b2, d2, f3, f4, e2, f2, e1, d1, g1, f1, j1, h1, k1, l1, a7, a5, a6, a4, a3, a2, c1, b1 179, 180, 181, 182, 183, 184, 185, 187, 198, 200, 201, 202, 203, 204, 205, 206, 243, 244, 245, 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197 sti0 -31 serial input streams 0 to 31 (5 v-tolerant inputs with enabled internal pull-downs) the data rate of each input stream can be selected independently using the stream input control r egisters (sicr[n] ). in the 2.048 mbps mode, these pins accept se rial tdm data streams at 2.048 mbps with 32 channels per frame. in the 4.096 mbps mode, these pins accept serial tdm data streams at 4.096 mbps with 64 channels per frame. in the 8.192 mbps mode, these pins accept serial tdm data streams at 8.192 mbps with 128 channels per frame. in the 16.384 mbps mode, these pins accept tdm data streams at 16.384 mbps with 256 channels per frame. n4, p4, r4, p5, n13, p11, r14, r15, m15, l15, l13, l14, e14, d13, d15, c15, d16, e16, c16, b16, a13, a12, a10, a11, n1, m1, p1, r1, t2, t3, t5, t4 6, 7, 9, 10, 51, 52, 53, 54, 70, 72, 73, 74, 115, 116, 117, 118, 125, 126, 127, 128, 129, 130, 131, 132, 253, 254, 255, 256, 1, 2, 3, 4 stio0 - 31 serial output streams 0 to 31 (5 v-tolerant slew-rate-limited three-state i/os with enab led internal pull-downs) the data rate of each output stream can be selected independently using the stream output control registers (socr[n]). in the 2.048 mbps mode, these pins output serial tdm data streams at 2.048 mbps with 32 channels per frame. in the 4.096 mbps mode, these pins output serial tdm data streams at 4.096 mbps with 64 channels per frame. in the 8.192 mbps mode, these pins output serial tdm data streams at 8.192 mbps with 128 channels per frame. in the 16.3 84 mbps mode, these pins output serial tdm data streams at 16. 384 mbps with 256 channels per frame. these output streams can be used as bi-directionals by programming bdh (bit 7) and bdl (bit 6) of internal mode selection (ims) register. r3, p6, r5, n5, p12, n15, p13, p15, n16, m16, l16, k16, h16, j16, g16, f16 11, 12, 13, 14, 55, 56, 58, 59, 75, 76, 77, 78, 119, 120, 122, 124 stohz0 - 15 serial output streams high impedance control 0 to 15 (5 v-tolerant slew-rate-li mited three-state outputs) these pins are used to enable (or disable) external three-state buffers. when an output channel is in the high impedance state, the stohz drives high for the dur ation of the corresponding output channel. when the stio channel is active, the stohz drives low for the duration of the corres ponding output channel. stohz outputs are available for stio0 - 15 only. pbga pin number lqfp pin number pin name description
zl50018 data sheet 19 zarlink semiconductor inc. b15 141 ode output drive enable (5 v-tolerant input with internal pull-up) this is the output enable control for stio0 - 31 and the output-driven-high control for stoh z0 - 15. when it is high, stio0 - 31 and stohz0 - 15 are enabled. when it is low, stio0 - 31 are tristated and stohz0 - 15 are driven high. m4, n6, r6, p7, r7, n7, m8, n8, p8, r8, m9, n9, r9, n10, p9, r10 16, 18, 20, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 36, 37, 38 d0 - 15 data bus 0 to 15 (5 v-tolerant slew-rate-limi ted three-state i/os) these pins form the 16-bit da ta bus of the microprocessor port. n12 44 dta _rdy data transfer acknowledgment_ready (5 v-tolerant three-state output) this active low output indicates that a data bus transfer is complete for the motorola interface. for the intel interface, it indicates a transfer is completed when this pin goes from low to high. an external pull-up resistor must hold this pin at high level for the motorola mode. an external pull-down resistor must hold this pin at low level for the intel mode. r11 40 cs chip select (5v-tolerant input) active low input used by the motorola or intel microprocessor to enable the microprocessor port access. n11 39 r/w _wr read/write_write (5 v-tolerant input) this input controls the directio n of the data bus lines (d0 - 15) during a microprocessor access. fo r the motorola interface, this pin is set high and low for the read and write access respectively. for the intel interface, a write ac cess is indicated when this pin goes low. r12 42 ds _rd data strobe_read (5 v-tolerant input) this active low input works in conjunction with cs to enable the microprocessor port read and wr ite operations for the motorola interface. a read access is indicated when it goes low for the intel interface. k13, k15, k14, j11, j12, j13, j15, h11, j14, h12, h13, h15, g12, g13 82, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 96, 98, 99 a0 - 13 address 0 to 13 (5 v-tolerant inputs) these pins form the 14-bit addres s bus to the internal memories and registers. pbga pin number lqfp pin number pin name description
zl50018 data sheet 20 zarlink semiconductor inc. 3.0 device overview the device has thirty-two st-bus/gci-bus inputs (sti0 - 31) and thirty-two st-bus/gci-bus outputs (stio0 - 31). stio0 - 31 can also be configured as bi-directional pins, in which case sti0 - 31 will be ignored. it is a non-blocking digital switch with 2048 64 kbps channels and is capabl e of performing rate conversion between st-bus/gci-bus inputs and st-bus/gci-bus outputs. the st-bus/gci-bus inputs accept serial input data streams with data rates of 2.048, 4.096, 8.192 and 16.384 mbps on a per-stream basis. the st-bus/gci-bus outputs deliver serial data streams with data rates of 2.048, 4.096, 8.192 and 16.3 84 mbps on a per-stream basis. the device also provides sixteen high impedance control outputs (stohz0 - 15) to support the use of external st-bus/gci-bus tristate drivers for the first sixteen st-bus/gci-bus outputs (stio0 -15). by using zarlink?s message mode capability, microproc essor data stored in the connection memory can be broadcast to the output streams on a pe r-channel basis. this feature is usef ul for transferring control and status information for external circuits or other st-bus/gci-bus devices. the device uses the st-bus/gci-bus input frame pulse (f pi) and the st-bus/gci-bus input clock (cki) to define the input frame boundary and timing for sampling the st-bus/gci-bus input st reams with various data rates. the output data streams will be driven by and have thei r timing defined by fpi and cki in divided slave mode. in multiplied slave mode, the ou tput data streams will be dr iven by an inte rnally generated clock, which is multiplied from cki internally. in master mode, the on-chip dpll wi ll drive the output data stre ams and provide output clocks and frame pulses. refer to application note zlan-120 for further explanation of the different modes of operation. when the device is in master mode, the dpll is phas e-locked to one of four dpll reference signals, ref0 - 3, which are sourced by an external 8 khz, 1.544 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz or 19.44 mhz reference signal. the on-chip dpll also offe rs jitter attenuation, reference switching, reference monitoring, freerun and holdover function s. the jitter performance exceeds the stratum 3 specification. the intrinsic jitter of all output clocks is less than 1 ns (except for the 1.544 mhz output). there are two slave modes for this device: the first is the divided slave mode. in this mode, out put streams are clocked by in put cki. therefore the output streams have exactly the same jitter as the input streams. the output data ra te can be the same as or lower than m13 41 mot_intel motorola_intel (5 v-tolerant input with internal pull-up) this pin selects the motorola or intel microprocessor interface to be connected to the device. when this pin is unconnected or connected to high, motorola interfac e is assumed. when this pin is connected to ground, intel interface should be used. p10 43 irq interrupt (5 v-tolerant three-state output) this programmable active low output indicates that the internal operating status of the dpll has changed. an external pull-up resistor must hold this pin at high level. g2 211 reset device reset (5 v-tolerant input with internal pull-up) this input (active low) puts the device in its reset state that disables the stio0 - 31 drivers and drives the stohz0 - 15 outputs to high. it also preloads registers with default values and clears all internal counters. to en sure proper reset action, the reset pin must be low for longer than 1 s. upon releasing the reset signal to the device, the first mi croprocessor access cannot take place for at least 600 s due to the time required to stabilize the device and the crystal oscillator from the power-down state. refer to section section 17.2 on page 48 for details. pbga pin number lqfp pin number pin name description
zl50018 data sheet 21 zarlink semiconductor inc. the input data rate, but the output dat a rate cannot be higher than what ck i can drive. for example, if cki is 4.096 mhz, the output data rate cannot be higher than 2.048 mbps. the second slave mode is called multiplied slave mode. in this mode, cki is used to generate a 16.3 84 mhz clock internally, and output streams are driven by this 16.384 mhz clock. in multiplied slave mode, the data rate of output streams can be any rate, but output jitter may not be exactly the same as input jitter. a motorola or intel compatible non-multiplexed microproce ssor port allows users to pr ogram the device to operate in various modes under different swit ching configurations. users can use the microprocessor port to perform internal register and memory read a nd write operations. the microprocessor port has a 16-bit data bus, a 14-bit address bus and six control signals (mot_intel , cs , ds _rd , r/w _wr , irq and dta _rdy). the device supports the mandatory requirements of the ieee-1149.1 (j tag) standard via the test port. 4.0 data rates and timing the zl50018 has 32 serial data inputs and 32 serial data outputs. each stream can be individually programmed to operate at 2.048, 4.096, 8.192 or 16.384 mbps. depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 s frame. the output streams can be programmed to operate as bi-d irectional streams. the output streams are divided into two groups to be programmed into bi-directional mode. by setting bdl (bit 6) in the internal mode selection (ims) register, input streams 0 - 15 (sti0 - 15) are internally tied low, and output streams 0 - 15 (stio0 - 15) are set to operate in a bi-directional mode. similarly, when bdh (bit 7) in the internal mode sele ction (ims) register is set, input streams 16 - 31 (sti16 - 31) are internally tied lo w, and output streams 16 - 31 (s tio16 - 31) are set to operate in bi-directional mode. the groups do not have to be set into the same mode. therefore it is possible to have half of the streams operating in bi-directional mode while the ot her half is operating in normal input/output mode. the input data rate is set on a per-stream basis by progr amming stin[n]dr3 - 0 (bits 3 - 0) in the stream input control register 0 - 31 (sicr0 - 31). the output data ra te is set on a per-stream basis by programming sto[n]dr3 - 0 (bits 3 - 0) in the stream output control register 0 - 31 (socr0 - 31). the output data rates do not have to match or follow the input data rates. the maximum number of channels switched is limited to 2048 channels. if all 32 input streams were operating at 16.384 mbps (256 channels per stream), this would result in 8192 channels. memory limitations prevent the device from operating at this capacity. a maximum capacity of 2048 channels will occur if eight of the streams are oper ating at 16.384 mbps, half the stream s are operating at 8.192 mbps or all streams operating at 4.096 mbps. with all streams oper ating at 2.048 mbps, the capacity will be reduced to 1024 channels. however, as each stream can be programmed to a different data rate, any comb ination of data rates can be achieved, as long as the total channel count does not exceed 2048 channels. it s hould be noted that only full stream can be programmed for use. the device does not allow fractional streams. 4.1 external high impe dance control, stohz0 - 15 there are 16 external high impedance control signals, stohz0 - 15, that are used to cont rol the external drivers for per-channel high impedance operations. only the first sixteen st-bus/gci-bus (stio0 - 15) outputs are provided with corresponding stohz signals. the stohz outputs deliver the appropriate num ber of control timeslot channels based on the output stream data rate. each contro l timeslot lasts for one channel time. when the ode pin is high and the osb (bit 2) of the control register (cr) is also high, stohz0 - 15 are enabled. when the ode pin, osb (bit 2) of the control register (cr) or the reset pin is low, stohz0 - 15 are dr iven high, together with all the st-bus/gci-bus outputs being tristated. under normal operation, the correspondi ng stohz outputs of any unused st-bus/gci-bus channel (high impedance) are driven high. refer to figure 18 on page 33.
zl50018 data sheet 22 zarlink semiconductor inc. 4.2 input clock (cki) and input frame pulse (fpi) timing the input clock for the z l50018 can be arranged in one of three different ways. these different ways will be explained further in section 11.1 to se ction 11.3 on page 38. depending on the m ode of operation, the input clock, cki, will be based on the highest data rate of either the input or both the input and output data rate s. the user has to program the ckin1 - 0 (bits 6 - 5) in the control register (cr) to indicate the width of the input frame pulse and the frequency of the input cl ock supplied to the device. in master mode and divided slave mode, the input clock, cki, must be at least twice the highest input or output data rate. for example, if the highes t input data rate is 4.096 mbps and the highest output data rate is 8.192 mbps, the input clock, cki, must be 16.384 mh z, which is twice the highest overall data rate. the only exception to this is for 16.384 mbps input or output data. in this case, the inpu t clock, cki, is equal to the data rate. the input frame pulse, fpi, must always follow cki. in master mode, cko2 and fpo2 can be programmed to be us ed as cki and fpi by setting cki_lp (bit 10) in the control register (cr). this will internally loop back the cko2 and fpo2 timing. when this bit is set, cki and fpi must be tied low or high externally. in multiplied slave mode, the input clock, cki, must be at least twice the hi ghest input data rate, regardless of the output data rate. following the example above, if the hi ghest input data rate is 4.096 mbps, the input clock, cki, must be 8.192 mhz, regardless of the out put data rate. the only exception to this is for 16.384 mbps input data. in this case, the input clock, cki, is equal to the data rate. the input frame pulse, fpi, must always follow cki. the zl50018 accepts positive and negative st-bus/gci-bus input clock and input frame pulse formats via the programming of ckinp (bit 8) and fpinp (bit 7) in the control register (cr). by def ault, the device accepts the negative input clock format and st-bus format frame pulses . however, the switch can al so accept a positive-going clock format by programming ckinp (bit 8) in the cont rol register (cr). a gci-bus format frame pulse can be used by programming fpinpos (bit 9) and fpin p (bit 7) in the co ntrol register (cr). highest input or output data rate ckin 1-0 bits input clock rate (cki) input frame pulse (fpi) 16.384 mbps or 8.192 mbps 00 16.384 mhz 8 khz (61 ns wide pulse) 4.096 mbps 01 8.192 mhz 8 khz (122 ns wide pulse) 2.048 mbps 10 4.096 mhz 8 khz (244 ns wide pulse) table 1 - cki and fpi configurations for master and divided slave modes highest input data rate ckin 1-0 bits input clock rate (cki) input frame pulse (fpi) 16.384 mbps or 8.192 mbps 00 16.384 mhz 8 khz (61 ns wide pulse) 4.096 mbps 01 8.192 mhz 8 khz (122 ns wide pulse) 2.048 mbps 10 4.096 mhz 8 khz (244 ns wide pulse) table 2 - cki and fpi configurat ions for multiplied slave mode
zl50018 data sheet 23 zarlink semiconductor inc. figure 4 - input timing when ckin1 - 0 bits = ?10? in the cr figure 5 - input timing when ckin1 - 0 bits = ?01? in the cr fpi (244 ns) fpinp = 0 fpinpos = 0 fpi (244 ns) fpinp = 1 fpinpos = 0 fpi (244 ns) fpinp = 0 fpinpos = 1 fpi (244 ns) fpinp = 1 fpinpos = 1 cki (4.096 mhz) ckinp = 0 cki (4.096 mhz) ckinp = 1 76 1 0 0 7 sti (2.048 mbps) channel 0 channel 31 st-bus gci-bus fpi (122 ns) fpinp = 0 fpinpos = 0 fpi (122 ns) fpinp = 1 fpinpos = 0 fpi (122 ns) fpinp = 0 fpinpos = 1 fpi (122 ns) fpinp = 1 fpinpos = 1 cki (8.192 mhz) ckinp = 0 cki (8.192 mhz) ckinp = 1 sti (4.096 mbps) channel 0 channel 63 6 54 1 0 2 76 7 1 0 st-bus gci-bus
zl50018 data sheet 24 zarlink semiconductor inc. figure 6 - input timing when ckin1 - 0 = ?00? in the cr 5.0 st-bus and gci-bus timing the zl50018 is capable of operating using either the st -bus or gci-bus standards. the output timing that the device generates is defined by the bus standard. in th e st-bus standard, the output frame boundary is defined by the falling edge of cko while fpo is low. in the gci-bu s standard, the frame boundary is defined by the rising edge of cko while fpo goes high. the data rates define the number of channels that are available in a 125 s frame pulse period. by default, the zl50018 is configured for st-bus input and output timing. to se t the input timing to conform to the gci-bus standard, fpinpos (bit 9) and fpinp (bit 7) in the control register (cr) must be set. to set output timing to conform to the gci-bus standard, fpo[n]p and fpo[n]po s must be set in the output clock and frame pulse selection register (ocfsr). the cko[n]p bits in the ou tput clock and frame pulse selection register control the polarity (positive-going or negat ive-going) of the output clocks. 6.0 output timing generation the zl50018 generates frame pulse and clock timing. there ar e five output frame pulse pins (fpo0 - 3, 5) and six output clock pins (cko0 - 5). all output frame pulses are 8 khz output signals. by default, the output frame boundary is defined by the falling edge of the cko0, while fpo0 is low. at the out put frame boundary, the cko1, cko2 and cko3 output cloc ks will by default have a fall ing edge, while fpo1, fpo2 and fpo3 will be low. at the output frame boundary, cko4 will by default have a falling edge while fp o0 is low (cko4 has no corresponding output frame pulse). at t he output frame boundary, cko5 will by default have a rising edge while fpo5 (fpo_off2) will be low. the duration of the fram e pulse low cycle and th e frequency of the corresp onding output clock are shown in table 3 on page 25. every frame pulse and cloc k output can be tristated by programming the enable bits in the internal mode selection (ims) register. fpi (61 ns) fpinp = 0 fpinpos = 0 fpi (61 ns) fpinp = 1 fpinpos = 0 fpi (61 ns) fpinp = 0 fpinpos = 1 fpi (61 ns) fpinp = 1 fpinpos = 1 cki (16.384 mhz) ckinp = 0 cki (16.384 mhz) ckinp = 1 sti (8.192 mbps) channel 0 channel n = 127 6 5 4 3 2 1 3 2 1 0 5 4 7 6 5 7 1 0 sti (16.384 mbps) channel 0 channel n = 255 6 7 4 5 2 3 0 1 6 7 4 5 2 3 2 3 0 1 6 7 4 5 2 3 6 7 4 5 2 3 0 1 2 3 0 1 st-bus gci-bus
zl50018 data sheet 25 zarlink semiconductor inc. the output timing is dependent on the oper ation mode that is selected. when t he device is in divided slave mode, the frequencies on cko0 - 3 cannot be greater than the input cl ock, cki. for example, if the input clock is 8.192 mhz, the cko2 pin will not produce a valid output cl ock and the cko3 pin can only be programmed to output a 4.096 mhz or 8.192 mhz clock signa l. the output clocks cko4 - 5 will not generate valid outputs unless the slv_dpllen (bit 13) of the control register (cr) is set. in master mode there are programmable output frame pu lse, fpo3, and clock pins, cko3 and cko4. the outputs from fpo3 and cko3 are programmed by the ckofpo3se l1 - 0 (bits 13 - 12) in the output clock and frame pulse selection (ocfsr) register. the output clock pin, ck o4, is controlled by setting the cko4sel (bit 14) in the ocfsr register. in multiplied slave mode, cko4 and cko5 are not availabl e unless slv_dpllen is set in the control register. all other clocks and frame pulses correspond to the timing shown in table 3 above. the device also delivers positive or negative output frame pulse and st-bus/gci-bus output clock formats via the programming of various bits in the output clock and frame pulse selecti on register (ocfsr). by default, the device delivers the negative output clock format. the zl 50018 can also deliver gci-bu s format output frame pulses by programming bits of the output clock and frame pulse selection register (ocfsr). as there is a separate bit setting for each frame pulse output, some of the output s can be set to operate in st-bus mode and others in gci-bus mode. the following figures describe the usa ge of the fpo0p, fpo1p, fpo2p, fpo3p, cko0p, cko1p, cko2p, cko3p, cko4p and cko5p bits to generate the fpo0 - 3 and cko0 - 5 timing. fpo_off2 is configured to provide the non-offset frame pulse corresponding to the 19.44 mhz clock on cko5 by setting the fp19en (bit 10) in the fpoff2 register. in this instance, fpo_off2 can be labeled as fpo5. pin name output timing rate output timing unit fpo0 pulse width 244 ns cko0 4.096 mhz fpo1 pulse width 122 ns cko1 8.192 mhz fpo2 pulse width 61 ns cko2 16.384 mhz fpo3 pulse width 244, 122, 61 or 30 ns cko3 4.096, 8.192, 16.384 or 32.768 mhz cko4 1.544 or 2.048 mhz fpo5 pulse width 51 ns cko5 19.44 mhz table 3 - output timing generation
zl50018 data sheet 26 zarlink semiconductor inc. figure 7 - output timing for cko0 and fpo0 figure 8 - output timing for cko1 and fpo1 ckofpo0en = 1 fpo0p = 0 fpo0pos = 0 ckofpo0en = 1 fpo0p = 1 fpo0pos = 0 ckofpo0en = 1 fpo0p = 0 fpo0pos = 1 ckofpo0en = 1 fpo0p = 1 fpo0pos = 1 ckofpo0en = 1 cko0p = 0 cko0 = 4.096 mhz ckofpo0en = 1 cko0p = 1 cko0 = 4.096 mhz st-bus gci-bus ckofpo1en = 1 fpo1p = 0 fpo1pos = 0 ckofpo1en = 1 fpo1p = 1 fpo1pos = 0 ckofpo1en = 1 fpo1p = 0 fpo1pos = 1 ckofpo1en = 1 fpo1p = 1 fpo1pos = 1 ckofpo1en = 1 cko1p = 0 cko1 = 8.192 mhz ckofpo1en = 1 cko1p = 1 cko1 = 8.192 mhz st-bus gci-bus
zl50018 data sheet 27 zarlink semiconductor inc. figure 9 - output timing for cko2 and fpo2 figure 10 - output timing for cko3 and fpo3 with ckofpo3sel1-0=?11? ckofpo2en = 1 fpo2p = 0 fpo2pos = 0 ckofpo2en = 1 fpo2p = 1 fpo2pos = 0 ckofpo2en = 1 fpo2p = 0 fpo2pos = 1 ckofpo2en = 1 fpo2p = 1 fpo2pos = 1 ckofpo2en = 1 cko2p = 0 cko2 = 16.384 mhz ckofpo2en = 1 cko2p = 1 cko2 = 16.384 mhz st-bus gci-bus ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 0 fpo3pos = 0 ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 1 fpo3pos = 0 ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 0 fpo3pos = 1 ckofpo3en = 1 ckofpo3sel1-0 = 11 fpo3p = 1 fpo3pos = 1 ckofpo3en = 1 ckofpo3sel1-0 = 11 cko3p = 0 cko3 = 32.768 mhz ckofpo3en = 1 ckofpo3sel1-0 = 11 cko3p = 1 cko3 = 32.768 mhz note: when ckofpo3sel1-0 = ?00,? the output for fpo3 and cko3 follow the same as figure 7: output timing for cko0 and fpo0 when ckofpo3sel1-0 = ?01,? the output for fpo3 and cko3 follow the same as figure 8: output timing for cko1 and fpo1 when ckofpo3sel1-0 = ?10,? the output for fpo3 and cko3 follow the same as figure 9: output timing for cko2 and fpo2 st-bus gci-bus
zl50018 data sheet 28 zarlink semiconductor inc. figure 11 - output timing for cko4 figure 12 - output timing for cko5 and fpo5 (fpo_off2) ckofpo0en = 1 fpo0p = 0 fpo0pos = 0 ckofpo0en = 1 fpo0p = 1 fpo0pos = 0 ckofpo0en = 1 fpo0p = 0 fpo0pos = 1 ckofpo0en = 1 fpo0p = 1 fpo0pos = 1 cko4en = 1 cko4p = 1 cko4sel = 0 cko4 = 2.048 mhz ckofpo4en = 1 cko4p = 0 cko4sel = 0 cko4 = 2.048 mhz cko4en = 1 cko4p = 1 cko4sel = 1 cko4 = 1.544 mhz ckofpo4en = 1 cko4p = 0 cko4sel = 1 cko4 = 1.544 mhz note: while there is no frame pulse output directly tied to the cko4, the output clocks are based on the frame pulse generated by fpo 0. st-bus gci-bus fpo5 (fpo_off2) fp19en = 1 cko5en = 1 ck5 = 19.44 mhz
zl50018 data sheet 29 zarlink semiconductor inc. 7.0 data input delay and data output advancement various registers are provi ded to adjust the input delay and output advancement for each input and output data stream. the input bit delay and output bit advancement ca n vary from 0 to 7 bits for each individual stream. if input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. the sampling point can vary from 1/4 to 4/4 with a 1/4-bit in crement for all input streams unless the stream is operating at 16.384 mbps, in which case the fractional bit delay has a 1/2-bit increment. by default, the sampling point is set to the 3/4-bit location for non-16.384 mbps data rates and the 1/2-bit location for the 16.384 mbps data rate. the fractional output bit advancement ca n vary from 0 to 3/4 bits, again wi th a 1/4-bit increment unless the output stream is operating at 16.384 mbps, in which case the out put fractional bit advancem ent has a 1/2-bit increment from 0 to 1/2 bit. by default, there is 0 output bit advancement. although input delay or output advancem ent features are available on stream s which are operating in bi-directional mode it is not recommended, as it can easily cause bus co ntention. if users require this function, special attention must be given to the timing to en sure contention is minimized. 7.1 input bit delay programming the input bit delay programming feature provides us ers with the flexibility of hand ling different wire delays when designing with source str eams for different devices. by default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming st-bus formatting). the input delay is enabled by stin[n]bd2-0 (bits 8 - 6) in the stream input control register 0 - 31 (sicr0 - 31) as described in table 61 on page 93. the input bit delay can range from 0 to 7 bits. figure 13 - input bit delay timing diagram (st-bus) fpi sti[n] bit delay = 0 (default) channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 channel 2 2 1 0 4 3 last channel sti[n] bit delay = 1 channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 channel 2 2 1 0 4 3 last channel bit delay = 1 5 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively.
zl50018 data sheet 30 zarlink semiconductor inc. 7.2 input bit sampling point programming in addition to the input bit delay featur e, the zl50018 allows users to change the sampling point of the input bit by programming stin[n]smp 1-0 (bits 5 - 4) in the stream input control register 0 - 31 (sicr0 - 31). for input streams operating at any rate except 16.384 mbps, the defaul t sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. when the stream is operating at 16.384 mbps, the default sampling point is 1/2 bit and can be adjusted to a 4/4 bit position. figure 14 - input bit sampling point programming fpi sti[n] stin[n]smp1-0 = 01 (2, 4 or 8 mbps) channel 0 last channel sampling point = 1/4 bit sti[n] stin[n]smp1-0 = 10 2, 4 or 8 mbps stin[n]smp1-0 = 00 16mbps - default channel 0 last channel sampling point = 1/2 bit sti[n] stin[n]smp1-0 = 00 2, 4 or 8 mbps - default channel 0 last channel sampling point = 3/4 bit 1 0 7 6 2 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps mode respectively. sti[n] stin[n]smp1-0 = 11 2, 4 or 8 mbps stin[n]smp1-0 = 10 16mbps channel 0 last channel sampling point = 4/4 bit 5 1 0 7 6 5 1 0 7 6 5 1 0 7 6 2 5
zl50018 data sheet 31 zarlink semiconductor inc. the input delay is controlled by stin[n]bd2-0 (bits 8 - 6) to control the bit shift and stin[n]smp1 - 0 (bits 5 - 4) to control the sampling point in the stream i nput control register 0 - 31 (sicr0 - 31). figure 15 - input bit delay and factional sampling point 7.3 output advancement programming this feature is used to advance the output data of indi vidual output streams with respect to the output frame boundary. each output stream has its own bit advancem ent value which can be programmed in the stream output control register 0 - 31 (socr0 - 31). by default, all output streams have ze ro bit advancement such that bit 7 is the first bit that appears after the output frame boundary (assuming st-bus format ting). the output advancement is enab led by sto[n]ad 2 - 0 (bits 6 - 4) of the stream output control register 0 - 31 (socr0 - 31) as described in table 63 on page 97. the output bit advancement can vary from 0 to 7 bits. figure 16 - output bit advancement timing diagram (st-bus) nominal channel n+1 boundary 7 6 5 4 3 2 1 0 7 0 000 01 000 10 000 00 (default) 000 11 001 01 001 10 001 00 001 11 010 01 010 10 010 00 010 11 011 01 011 10 011 00 011 11 111 00 111 10 111 01 110 11 110 00 110 10 110 01 101 11 101 00 101 10 101 01 100 11 100 00 100 10 100 01 111 11 the first 3 bits represent stin[n]bd2 - 0 for setting the bit delay. the second set of 2 bits represent stin[n]smp1 - 0 for setting the sampling point offset. sti[n] nominal channel n boundary example: with a setting of 011 10 the offs et will be 3 bits at a 1/2 sampling point. note: italic settings can be used in 16 mbps mode (1/2 and 4/4 sampling point). fpi stio[n] bit adv = 0 (default) channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 channel 2 2 1 0 4 3 last channel stio[n] bit adv = 1 channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 channel 2 2 1 0 3 last channel bit advancement = 1 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. 2 1
zl50018 data sheet 32 zarlink semiconductor inc. 7.4 fractional output bit advancement programming in addition to the output bit advanceme nt, the device has a fractional output bit advancement feature that offers better resolution. the fractional output bit advancement is useful in compensating for varying parasitic load on the serial data output pins. by default all of the streams have zero fr actional bit advancement such that bit 7 is the first bit that appears after the output frame boundary. the fractional output bit advancement is enabled by sto[n]fa 1 - 0 (bits 8 - 7) in the stream output control register 0 - 31 (socr0 - 31). fo r all streams running at any data rate except 16.384 mbps the fractional bit advancement can vary from 0, 1/4, 1/2 to 3/4 bits. fo r streams operating at 16.384 mbps, the fractional bit advancement can be set to either 0 or 1/2 bit. figure 17 - output fractional bit advancement timing diagram (st-bus) fpi stio[n] sto[n]fa1-0 = 00 (default) channel 0 7 last channel stio[n] sto[n]fa1-0 = 01 (2, 4 or 8 mbps) channel 0 last channel fractional bit advancement = 1/4 bit 6 5 2 1 0 stio[n] sto[n]fa1-0 = 10 (2, 4 or 8) sto[n]fa1-0 = 01 (16 mbps) channel 0 last channel fractional bit advancement = 1/2 bit stio[n] sto[n]fa1-0 = 11 (2, 4 or 8 mbps) channel 0 last channel fractional bit advancement = 3/4 bit note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. 7 6 5 1 0 7 6 5 1 0 7 6 5 1 0 4 4 4
zl50018 data sheet 33 zarlink semiconductor inc. 7.5 external high im pedance control advancement the external high impedance signals can be programmed to better match the timing required by the external buffers. by default, the output timing of the stohz signals follows the programmed channel delay and bit offset of their corresponding st-bus/gci-bus output streams. in add ition, for all high impedance streams operating at any data rate except 16.384 mbps, the user can advance the st ohz signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by programming stohz[n]a 2 - 0 (bit 11 - 9) in the stream output control r egister. when the stre am is operating at 16.384 mbps, the additional stohz advancement can be se t to 0, 1/2 or 4/4 bits by programming the same register. figure 18 - channel switching external high impedance control timing 8.0 data delay through the switching paths the switching of information from the i nput serial streams to the output seri al streams results in a throughput delay. the device can be programmed to perform timeslot in terchange functions with different throughput delay capabilities on a per-channel basis. for voice applications , select variable throughput delay to ensure minimum delay between input and output data. in wideband data applic ations, select constant delay to maintain the frame integrity of the information through the switch. the delay through the device varies according to the type of throughput delay selected by the v/c (bit 14) in the connection memory low when cmm = 0. 8.1 variable delay mode variable delay mode causes the output channel to be transmi tted as soon as possible. this is a useful mode for voice applications where the minimum throughput delay is mo re important than frame integrity. the delay through the switch can vary from 7 channels to 1 frame + 7 chan nels. to set the device into variable delay mode, varen (bit 4) in the control register (cr) must be set before v/c (bit 14) in the connection memory low when cmm = 0. if the varen bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. in variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. ch0 ch1 ch2 ch3 last-2 last-1 last ch0 last hiz fpi stio[n] stohz[n] stohz[n] (with advancement) (default = no advancement) stohz advancement (programmable in 4 steps of 1/4 bit for 2.048 mbps, 4.096 mbps and 8.192 mbps programmable in 2 steps of 1/2 bit for 16.384 mbps) note: n = 0 to 15 note: last = last channel of 31, 63, 127 and 255 for 2.048 mbps, 4.096 mbps. 8.192 mbps and 16.384 mbps modes respectively. output frame boundary
zl50018 data sheet 34 zarlink semiconductor inc. for example, if stream 4 channel 2 is switched to stream 5 channel 9 with variable dela y, the data will be output in the same 125 s frame. contrarily, if stream 6 channel 1 is sw itched to stream 9 channel 3, the information will appear in the following frame. figure 19 - data throughput delay for variable delay 8.2 constant delay mode in this mode, frame integrity is maintained in all switchin g configurations. the delay though the switch is 2 frames - input channel + output channel. this can re sult in a minimum of 1 frame + 1 chan nel delay if the last channel on a stream is switched to the first channel of a stream. the maximum delay is 3 frames - 1 channel. this occurs when the first channel of a stream is switched to the last channel of a stream. the cons tant delay mode is available for all output channels. the data throughput delay is expressed as a function of st-bus/gci-bus frames, input channel number (m) and output channel number (n). the data throughput delay (t) is: t = 2 frames + (n - m) the constant delay mode is controlled by v/c (bit 14) in the connection memory low when cmm = 0. when this bit is set low, the channel is in constant delay mode. if vare n (bit 4) in the control register (cr) is set (to enable variable throughput dela y on a chip-wide basis), the de vice can still be programmed to operate in c onstant delay mode. m = input channel number n = output channel number n-m <= 0 0 < n-m < 7 n-m = 7 n-m > 7 stio < sti stio >= sti t = delay between input and output 1 frame - (m-n) 1 frame + (n-m) n-m table 4 - delay for variable delay mode l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 sti4 ch2 stio5 ch9 sti6 ch1 stio9 ch3 frame n frame n + 1 l = last channel = 31, 63, 127, or 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps, or 16.384 mbps respectively.
zl50018 data sheet 35 zarlink semiconductor inc. figure 20 - data throughput delay for constant delay 9.0 connection memory description the connection memory consists of two blocks, connection memory low (cm_l) and connection memory high (cm_h). the cm_l is 16 bits wide and is used for channel switching and other special modes. the cm_h is 5 bits wide and is used for the voice coding function. when uaen (bit 15) of the connection memory low (cm_l) is low, -law/a-law conversion will be turn ed off and the contents of cm_h w ill be ignored. each connection memory location of the cm_l or cm_h can be read or written vi a the 16 bit microprocessor port within one microprocessor access cycle. see table 68 on page 100 for the address m apping of the connection memory. any unused bits will be reset to zero on the 16-bit data bus. for the normal channel switching operat ion, cmm (bit 0) of the connection memory low (cm_l) is programmed low. sca7 - 0 (bits 8 - 1) indicate the source (input) chann el address and ssa4 - 0 (bits 13 - 9) indicate the source (input) stream address. the 5-bit contents of the cm_h will be ignored during the normal channel switching mode without the -law/a-law conversion when uaen (bit 15) of t he connection memory low (cm_l) is set to zero. if -law/a-law conversion is required, t he cm_h bits must be programmed first to provide the voice/data information, the input coding law and the output coding law before t he assertion of uaen (bit 15) in the connection memory low. when cmm (bit 0) of the connection memory low (cm_l) is programmed high, the zl50018 will operate in one of the special modes described in table 70 on page 102. when the per-channel message mode is enabled, msg7 - 0 (bit 10 - 3) in the connection memory low (cm_l) will be output via the serial data stream as message output data. when the per-channel message mode is enabled, the -law/a-law conversion can also be enabled as required. l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 sti stio sti stio l = last channel = 31, 63, 127, or 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps, or 16.384 mbps respectively. frame n frame n + 1 frame n + 2
zl50018 data sheet 36 zarlink semiconductor inc. 10.0 connection memory block programming this feature allows for fast initialization of the conne ction memory after power up. 10.1 memory bloc k programming procedure 1. set mbpe (bit 3) in the control register (cr) from low to high. 2. configure bpd2 - 0 (bits 3 - 1) in the internal mode sele ction (ims) register to the desired values to be loaded into cm_l. 3. start the block progra mming by setting mbps (bit 0) in the internal mode selection register (ims) high. the val- ues stored in bpd2 - 0 will be loaded into bits 2 - 0 of all cm_l positions. the remaining cm_l locations (bits 15 - 3) and the programmable values in the cm_h (b its 4 - 0) will be load ed with zero values. the following tables show the resulting values that ar e in the cm_l and cm_h connection memory locations. note: bits 15 to 5 are reserved in connection memory high and should always be 0. it takes at least tw o frame periods (250 s) to complete a block program cycle. mbps (bit 0) in the control register (cr) will automatically reset to a low position after the block programming process has completed. mbpe (bit 3) in the internal mode sele ction (ims) register must be cleared from high to lo w to terminate the block programming process. this is not an automatic acti on taken by the device and must be performed manually. note: once the block program has been initiated, it can be terminated at any time prior to completion by setting mbps (bit 0) in the control register (cr) or mbpe (bit 3) in the internal mode selection (ims) register to low. if the mbpe bit was used to terminate the block programming, the mbps bit will have to be set low before enabling other device operations. bit1514131211109876543 2 1 0 value0000000000000bpd2bpd1bpd0 table 5 - connection memory low after block programming bit1514131211109876543 2 1 0 value0000000000000 0 0 0 table 6 - connection memory high after block programming
zl50018 data sheet 37 zarlink semiconductor inc. 11.0 device operation in master mode and slave modes this device has two main operating modes - master m ode and slave mode. each operating mode has different input/output clock and frame pulse setup requirements and usage. if the device is programmed to work in master mode, it is expected that the input clock and frame pulse will be supplied from the embedded dpll, either directly using the internal loopbac k mode or indirectly through external loopback path. sources and destinations of the device?s serial input and ou tput data, respectively, have to be synchronized with the device?s output clock and frame puls e. in master mode, output clocks and frame pulses are driven by the dpll and they are always av ailable with any of the specified frequencies. the device can also operate in two different slave modes : divided slave mode and mult iplied slave mode. in either slave modes, output clocks and frame pulses are generated based on cki and fpi. the difference is that, in divided slave mode, the output clocks and frame pulses ar e directly divided from cki/fp i, while in multiplied slave mode, the output clocks and frame pulses are generated from an internal high-speed clock synchronized to cki and fpi. therefore, in divided slave mode, the output cl ock rates cannot exceed the cki rate (the output data rates are also limited as per table 1), but in multiplied slave mode, all specified output clock rates and data rates are available on cko0-3 and stio0-31. the input data rate cannot exceed the cki rate in either slave modes, because input data are always sampled directly by cki. by default, cko4, cko5 and fpo5 are not available in slave mode, as the embedded dpll is disabled. however, the dpll can be activated even in slave mode by programming the slv dpllen bit in the control register. when the dpll is enabled in slave mode, cko4, cko5 and fp o5 are generated from the dpll synchronized to one of the ref0-3 inputs, while the other clocks, frame pulses , and input/output data are synchronized to cki/fpi. it basically creates two separate timing domains - one for the dpll, and one for data switch logic. the two can be totally asynchronous to each other. in th is case the dpll will be fully functio nal, including its cap ability of reference monitoring. note that an external oscillator is required whenever the dpll is used. table 7, ?zl50018 operating modes? on page 37 summarizes the different modes of operat ion available within the zl50018. each major mode has various associated minor mo des that are determined by setting the relevant input control pins and control register bits (table 18, ?control register (cr) bits? on page 55) indicated in the table. device input pins cr register output clock pins data pins operating mode control signal bits reference lock enabled clock source major minor osc_en mode_4m [1:0] osci cki opm [1:0] slv_dpllen cki_lp cko0-3 cko4-5 cko0-3 cko4-5 sti sto master cki 1 00 20 mhz 4/8/16 m 00 x 0 freerun, holdover or ref0-3 yes yes cki*( cko2 (dpll) loopback x 1 cko2 divided slave 4m 1 11 20mhz 4 m 01 1 x cki ref0-3 yes cki cko0-3 (cki) 8/16 m 00 8/16 m 4m 0 11 x 4 m x0 0 x no 8/16 m 00 8/16 m multiplied slave 4 m 1 11 20 mhz 4 m 11 1 cki mult ref0-3 yes cko0-3 (cki mult) 8/16 m 00 8/16 m 4m 0 11 x 4 m x1 0 x no 8/16 m 00 8/16 m legend: x - don?t care or not applicable. reference lock - refers to what signal the output pins are locked to: ref0-3 = normal mode cki = bypass. cki is passed directly through to cko0-3. cki mult = cki is passed through clock multiplier to cko0-3. * cki must be phase aligned (edge synchronous) to cko0-3. clock source - refers to which clock samples sti and which clock outputs sto; sti applies when sti or stio is input; sto applie s when stio is output. table 7 - zl50018 operating modes
zl50018 data sheet 38 zarlink semiconductor inc. 11.1 master mode operation when the device is in master mode, the dpll is phase-lo cked to the one of four dpll reference signals, ref0 to ref3, which are sourced by an external 8 khz, 1. 544 mhz, 2.048 mhz, 4.096 mh z, 8.192 mhz, 16.384 mhz or 19.44 mhz signal. the on-chip dpll also offers referenc e switching and monitoring, jit ter attenuation, freerun and holdover functions. in this mode, sti o0 - 31 are driven by a clock generated by the dpll, which also provides all the output clocks (cko0 - 5) and frame pulses (fpo0 - 3 and fpo_off0 - 2). one of the output clocks and frame pulses should be looped back to cki/fpi as reference for t he input data, either by internal loopback (by setting the cki_lp bit high in the control register) or through some ex ternal loopback paths. if external loopback is used, it is recommended that cko2 (16.384mhz) and fpo2 (61ns pulse) ar e used so that all input data rates are available. 11.2 divided slave mode operation when the device is in divided slave mode, stio0 - 31 ar e driven by cki. in this mode, the output streams and clocks have the same jitter characteristics as the inpu t clock (cki), but the input and output data rates cannot exceed the limit defined by cki (as per table 1). for exam ple, if cki is 4.096 mhz, t he input and output data rate cannot be higher than 2.048 mbps and the generated output clock rates cannot exceed 4.096 mhz. if the dpll is not enabled, an external oscillator is optional in divided slave mode. 11.3 multiplied slave mode operation when the device is in multiplied slave mode, device hardwar e is used to multiply cki internally. stio0 - 31 are driven by this internally generated clock. in this mode, the output clocks and data can run at any of the specified rates, but they may have different jitte r characteristics from the input clock (cki). the input data rates are still limited by the cki rate (as per table 1), as input data ar e always sampled directly by cki. if the dpll is not enabled, an external oscillator is not required in multiplied slave mode. 12.0 overall operation of the dpll the dpll accepts four input references and delivers si x output clocks and five output frame pulses. the dpll meets or exceeds all of the requirem ents of the telcordia gr-1244-core standard for a stratum 3 compliant pll. this includes the freerun, reference switching and mo nitoring, jitter/wander attenua tion and holdover functions. the intrinsic output jitter of the dpll does not exceed 1 ns (except for the 1.544 mhz output). the input locking range of the dpll is programmable, such that it can be larger than the strict stratum 3 requirements. the dpll is able to lock to an input reference presented on the ref0 - 3 inputs. it is possible to force the dpll module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun. while in freerun mode, the dpll is able to work in soft ware mode which allows the user to program an output frequency offset value through the microport of the dev ice. depending on the selected software mode, the dpll outputs can: a. gradually meet the given frequency offset (fol lowing pre-programmed phase alignment speed (phase slope) and internal filter response), or b. immediately, upon finishing the microport write, r each the given frequency offset, allowing an external filter to be used.
zl50018 data sheet 39 zarlink semiconductor inc. 12.1 dpll timing modes there are four functional modes for t he dpll: normal, holdover, automatic and freerun modes. in addition to these four functional modes, the dpll can also be programmed to internal reset mode. 12.1.1 normal mode in normal timing mode, the dpll generates clocks and frame pulses that are phase locked to the active input reference. jitter on the input clock is attenuated by the dpll. 12.1.2 holdover mode in holdover mode, the dpll no longer synchronizes the output clock to any input reference. it maintains the frequency that it was at prior to ent ering holdover mode. the holdover mode typically happens when the input clock becomes unreliable or is lost altogether. it takes some time for the system to realize that the input clock is unreliable. meanwhile, the dpll tracks an unreliable clo ck. therefore the dpll could hold to an invalid frequency when it enters holdover mode. in order to prevent this si tuation, the dpll stores t he current frequency at regular intervals in holdover memory so that it can restore the fr equency of the input clock just after the input clock became unreliable. the accuracy of the output clock with respect to the last valid input clock is subject to certain standards referred to as stratum levels where each level requires a certain accuracy. the standards ansi t1.101 and telcordia gr-1244-core specify the stratum level requirements. w here ansi just gives one total number, telcordia splits it into three components, thereby creating a more stringent requirement than ansi. in order to meet stratum 3, the holdover accuracy of the dpll is better than 0.05 ppm. note that in order for the system to meet stratum 3, the system clock provided by the external oscillat or must meet the requirements for the temperature dependence and drift. if stratum 3 accuracy is not required, a less stable and cheaper system clock can be used instead. 12.1.3 automatic mode in this mode, the state machine controls the dpll based on the settings in the regi sters and the quality of the reference input clocks. the dpll is internally either in normal or in holdover mode. in the following two sections, the reference selection and state machine operation in automatic mode will be explained in more details. 12.1.3.1 automatic reference switching without preferences when the dpll is programmed to operate in automati c mode without preference (rccr register, pms2-0 bits = 000), all references, ref0-3, will have equal importance. a circulating round robin selection sequence determines the reference to be used as shown in figur e 21. the state machine basically searches for valid reference in a circular order of ref0 -> ref1 -> ref2 -> ref3 -> ref0, etc.
zl50018 data sheet 40 zarlink semiconductor inc. figure 21 - automatic reference switching state diagram with no preferred reference 12.1.3.2 automatic reference switching with preference if a particular reference needs to have higher priority than the others, the device can be programmed in automatic mode with a preferred reference (rccr register, pms2-0 bits = 001). when a preferred reference is selected, the device can only switch automatically be tween two references, as shown in t able 8. the preferred reference will be used as the primary reference and, by default, only its next consecutive reference will be used as the secondary reference. no more than two references can be used in automatic mode when a preferred reference is selected. figure 22 shows the state diagram for the four valid opti ons of automatic reference switching with a preferred reference. primary reference (preferred) secondary reference option 1 ref 0 ref 1 option 2 ref 1 ref 2 option 3 ref 2 ref 3 option 4 ref 3 ref 0 table 8 - preferred reference selection options free run holdover 0 holdover 1 ref 0 ref 1 ref 3 ref 2 holdover 2 holdover 3 all ref failed ref 0 valid ref 0 failed all ref failed all ref failed all ref failed ref 1 valid ref 1 failed ref 2 valid ref 3 valid ref 2 failed ref 3 failed re f 2 v alid a nd ref 1 failed r e f 0 v a lid a n d r e f 3 f a ile d r e f 1 v a l i d a n d r e f 0 f a i l e d r e f 3 v a l i d a n d r e f 2 f a i l e d start ref 0 and 1 failed and (ref 2 or ref 3 valid) ref 2 and 3 failed and (ref 0 or ref 1 valid) ref 1 and 2 failed and (ref 3 or ref 0 valid) ref 3 and 0 failed and (ref 1 or ref 1 valid)
zl50018 data sheet 41 zarlink semiconductor inc. figure 22 - automatic reference switching state diagrams with preferred reference free run holdover 0 ref 0 ref 1 holdover 1 r e f 1 v a l i d a n d r e f 0 f a i l e d ref 1 failed or ref 0 valid ref 1 valid ref 0 valid preferred references: ref 0 ref 0 valid and ref 0 failed note: other combinations not shown here ar e invalid settings and should not be used dpll will switch between ref 0 and ref 1 ref 0 failed ref 0 and 1 failed ref 0 and 1 failed free run holdover 2 ref 2 ref 3 holdover 3 r e f 3 v a l i d a n d r e f 2 f a i l e d ref 3 failed or ref 2 valid ref 3 valid ref 2 valid preferred references: ref 2 ref 2 valid and ref 2 failed dpll will switch between ref 2 and ref 3 ref 2 failed ref 2 and 3 failed ref 2 and 3 failed free run holdover 1 ref 1 ref 2 holdover 2 r e f 2 v a l i d a n d r e f 1 f a i l e d ref 2 failed or ref 1 valid ref 2 valid ref 1 valid preferred references: ref 1 ref 1 valid and ref 1 failed dpll will switch between ref 1 and ref 2 ref 1 failed ref 1 and 2 failed ref 1 and 2 failed free run holdover 3 ref 3 ref 0 holdover 0 r e f 0 v a l i d a n d r e f 3 f a i l e d ref 0 failed or ref 3 valid ref 0 valid ref 3 valid preferred references: ref 3 ref 3 valid and ref 3 failed dpll will switch between ref 3 and ref 0 ref 3 failed ref 0 and 3 failed ref 0 and 3 failed preferred preferred preferred preferred start start start start option 1 option 2 option 3 option 4
zl50018 data sheet 42 zarlink semiconductor inc. with a preferred reference, if more th an two references are required, or the two references are not in consecutive order, or the roles of the two references need to be inte rchanged, then external software is required to manually control the reference switching of the dpll (by monitori ng the reference failure status and reprogramming the device accordingly). 12.1.4 freerun mode in freerun mode, the dpll generates a fixed output frequency based on the cr ystal oscillator and a programmed centre frequency. to meet stratum 3, the accuracy of t he circuitry for the freerunning output clock must be 4.6 ppm or better. the circuit?s freeru n accuracy is better than 0.003 ppm. in freerun mode, the dpll does not lock to any reference. it is important that the dev ice is not simultaneously in freerun mode (see the rccr register) and fast lock mode (s ee the bwcr register). ot herwise, the output frame pulse may not be generated correctly. 12.1.5 software controlled mode when the dpll is in the freerun mode, it can be put into software controlled mode by enabling the swe (bit 3) in the dpll control register (dpllcr). the software de lta frequency register (swdfr) contains the frequency offset to which the dpll outputs will move. if swf (bit 4) in the dpll control register (dpllcr) is low, the dpll outputs will gradually move to the given frequency offset, with the speed defined by the dpll internal filter and phase alignment speed (phase slope) limiter. if swf (bit 4) is high, the dpll outputs will reach the software delta frequency register (swdfr) frequency offs et immediately after it is written, allowing an external software-based filter and phase alignment speed (phase slope) limiter to be used. when swe (bit 3) is low or the dpll is not in the freerun mode, the value of software delta frequency regist er (swdfr) will be ignored. for detailed description of the dpll control register (dpllcr) bits and the soft ware delta frequency register (swdfr) bits see table 29 on page 65, and table 33 on page 70, respectively. 12.1.6 dpll internal reset mode dpll_irm (bit 0) in the dpll contro l register (dpllcr) enables the inter nal reset mode. in the internal reset mode, the dpll module is disabled to save power. the circuit will be reset continuo usly and no output clocks will be generated. when the internal dpll module is in the internal reset mode, all registers remain accessible. note that applying the dpll reset does not re set the dpll registers: they preserve the values that they had prior to entering reset. 13.0 dpll frequency behaviour 13.1 input frequencies the dpll is capable of synchronizing to one of the following input frequencies: 8khz 1.544 mhz (ds1) 2.048 mhz (e1) 4.096 mhz 8.192 mhz 16.384 mhz 19.44 mhz table 9 - dpll input reference frequencies
zl50018 data sheet 43 zarlink semiconductor inc. 13.2 input frequencies selection the input frequencies of ref 0 - 3 can be automatically detected or programmed indep endently by the reference frequency register (rfr) if rfre (bit 1) in the dpll control register (dpllcr) is set. the detected frequency of the selected reference is indicated in the reference c hange status register (rcsr) . in addition, the detected frequencies of all four references ar e indicated in the reference frequency status register (rfsr). see table 29 on page 65, table 30 on page 67, table 41 on page 76 and tabl e 59 on page 91 for the detailed bit description of the dpll control register (dpllcr), reference frequency register (rfr), reference change status register (rcsr) and reference frequency status register (rfsr), respectively. 13.3 output frequencies the dpll generates a limited number of output signals. all signals are synchronous to each other and in the normal operating mode, are locked to the selected input re ference. the dpll provides outputs with the following frequencies: 13.4 pull-in/hold-in ra nge (also called locking range) the widest tolerance required for any of the given input clock frequencies is 130 ppm for the t1 clock (1.544 mhz). if the system clock (crystal/oscillator) accuracy is 30 ppm, it requires a minimum pull-in range of 160 ppm. users who do not require the 30 ppm freerun accuracy of the dpll can use a 100 ppm system clock. therefore the pull-in range is a minimal 230 ppm. the pull-in range is pr ogrammable through the frequency locking range register (flrr) as described in table 35 on pa ge 71. since the width of the register is 14 bits, the maximum programmable pull-in range can be as high as 372 ppm. the minimum pull-in/hold-in range required for stratum 3 clocks is 4.6 ppm. the default pull-in range of this device is 20 ppm. cko0 4.096 mhz cko1 8.192 mhz cko2 16.384 mhz cko3 4.096 mhz, 8.192 mhz, 16.384 mhz or 32.768 mhz cko4 1.544 mhz or 2.048 mhz cko5 19.44 mhz fpo0 8 khz (244 ns wide pulse) fpo1 8 khz (122 ns wide pulse) fpo2 8 khz (61 ns wide pulse) fpo3 8 khz (122 ns, 61 ns or 30 ns wide pulse) fpo5 8 khz (51 ns wide pulse) table 10 - generated output frequencies
zl50018 data sheet 44 zarlink semiconductor inc. 14.0 jitter performance 14.1 input clock cycle to cycle timing variation tolerance the zl50018 has an exceptional cycle to cycle timing variation tolerance of 20 ns. this allows the zl50018 to synchronize off a low cost dpll when it is in ei ther divided slave mode or multiplied slave mode. 14.2 input jitter acceptance the input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the input clock that the dpll must accept without making cycle slips or losing lo ck. the lower the jitter frequency, the larger the jitter acceptance. for jitter frequencies below a tenth of the cut-off frequency of the dpll's jitter transfer function, it safely can be said that an y provided input jitter will be followed by the dpll. the maximum value of jitter tolerance for the dpll is 1023 ui p-p . 14.3 jitter transfer function the corner frequency (-3 db) of the dpll is programmable through lpf (bits 3 - 0) in the bandwidth control register (bwcr) from 0.475 hz to 15.5 khz, in 16 steps. stratum 3 requires a corner frequency of maximally 3 hz. the default corner frequency is 1.9 hz. 15.0 dpll specific functions and requirements 15.1 lock detector to determine if the dpll is locked to the input clock, a lock detector moni tors the phase value output of the phase detector, which represents the difference between input re ference and output feedback clock. if the phase value is below a certain threshold for a certain interval, the dpll is pronounced locked to the input clock. the monitoring is done in intervals of 4ms. the lock detector threshold and the interval are programmabl e by the user through the lock detector threshold register (ldtr) and the lock de tector interval register (ldir) respectively. see table 36 on page 72 and table 37 on page 72 for the bit de scriptions of the lock de tector threshold register (ldtr) and lock detector interval register (ldir) respectively. the value of the lock detector threshold register (ldtr) should be programmed with respect to the maximum expected jitter frequency and amplitude on the selected input references. the lock status can be monitored through the refer ence change status register (rcsr). see table 41 on page 76 for the bit description of the re ference change status register (rcsr). 15.2 maximum time interval error (mtie) several standards require that the output clock of the dpll may not move in phase more than a certain amount. in order to meet those standards, a special circuit maintain s the phase of the dpll output clock during reference and mode rearrangements. the total output phase change or maximum timing interval error (mtie) during rearrangements is less than 31 ns per rearrangement, exc eeding stratum 3 requirements. after a large number of reference switches, the accumulated phase error can become significant, so it is recommended to use mtie reset in such situations, to realign outputs to the neares t edge of the selected reference. the mtie reset can be programmed by setting mtr (bit 7) in the reference c hange control register (rccr), as described in table 40 on page 75. 15.3 phase alignment speed (phase slope) besides total phase change, standards also require a cert ain rate of the phase change of the output clock. the phase alignment speed is programmable by the user thr ough a value in the slew rate limit register (srlr) as described in table 38 on page 73. stratum 3 requires that the phase alignment speed not exceed 81 ns per
zl50018 data sheet 45 zarlink semiconductor inc. 1.326 ms (61 ppm). the width of the r egister and the limiter circuitry, if not bypassed, provide a maximum phase change alignment speed of 186 ppm. the limiter circuitry can be bypassed by programming blm (bit 13) in the bandwidth control register (bwcr). bypassing limiter (combined with choice of other paramete rs in the bwcr register) can achieve very fast lock of the output clock to the selected input reference. a side effect of the bypa ssing limiter is manifested through much higher intrinsic jitter. once the bypa ssing is stopped, the jitter characteri stics are guaranteed. the phase alignment speed default value is 56 ppm. 15.4 fast locking mode if very fast locking feature (i.e., locking time in order of 1 s) is desirable, the bandwidth control register (bwcr) can be programmed to accommodate the feature for any selected corner frequency. in this mode, the dpll?s phase alignment speed limiter is bypassed. see table 39, ?b andwidth control register (bwcr) bits? on page 73. semi-fast locking mode does not bypass the internal phase alignment speed limiter, thereby maintaining phase alignment speed. this mode can be achieved by progra mming the sm_fst bit in the dpll control register. in freerun mode, the dpll does not lock to any reference. it is important that the dev ice is not simultaneously in freerun mode (see the rccr register) and fast lock mode (s ee the bwcr register). ot herwise, the output frame pulse may not be generated correctly. 15.5 reference monitoring the quality of the four input reference clocks is continuously monito red by the reference monitors. there are separate reference monitor circuits for the four dpll references. references are checked for short phase (single period) deviations as well as for frequency (m ulti-period) de viations with hysteresis. the reference status register (rsr) reports the status of the reference monitors. the register bits are described in table 57 on page 88. the reference mask register (rmr) allows users to ignore the monitoring features of the reference monitors. see table 58 on page 89 for details. 15.6 single period reference monitoring values for short phase deviations (upper and lower limit) are programmable throug h registers. the unit of the binary values of these numbers is 100 mhz cl ock period (10 ns). single per iod deviation limits are more relaxed than multi period limits, and are used for early detectio n of the reference loss, or huge phase jumps. registers containing the lower and upper limits of the ac ceptance range for the single input reference period measurement are: reference lower limit registers: r0llr, r1llr, r2llr and r3llr and the reference upper limit registers: r0ulr, r1ulr, r2ulr and r3ulr. the default values for the upper and lower limits are shown in the following table: reference frequency comment 8 khz 10 ui p-p 1.544 mhz 0.3 ui p-p 2.048 mhz 0.2 ui p-p 4.096 mhz 0.2 ui p-p 8.192 mhz 0.2 ui p-p 16.384 mhz 0.2 ui p-p 19.44 mhz 0.2 ui p-p table 11 - values for single period limits
zl50018 data sheet 46 zarlink semiconductor inc. 15.7 multiple period reference monitoring to monitor reference failure based on frequency offset, mu lti period checking is perf ormed. reference validation time is prescribed by telcordia gr-1244-core and is between 10 and 30 seconds. to meet the criteria for reference validation time, the time base for multi perio d monitoring has to be big enough and is programmable. to implement hysteresis, the upper limits are split into near upper and far upper limits and the lower limits are split into near lower and far lower limits. the reference failure is detectable only when the reference passes far limits, but passing is not detected until the reference is within near limits. the zone between near and far limits, called the ?grey zone?, is required by standards and prevents unnece ssary reference switching when the selected reference is close to the boundary of failure. the monitor makes a decision about reference validity after two consecutive measurements with respect to its time base. the time base for multi-period monitoring, by defaul t, is 10 seconds. the time base is defined in the number of reference clock cycles and is programmable. assuming that the evaluation time is chosen to be the same regardless of reference frequency (10 seconds), the parameters that allow hysteresis functionality also have the same values, regardless of the reference frequency. these parameters (near lower, far lower, near upper and far upper limits) are programmable. registers containing the multi period count are: refere nce multi-period counter registers: r0mpcrl, r0mpcru, r1mpcrl, r1mpcru, r2mpcrl, r2mpcru, r3mpcrl and r3mpcru. for the measurement length of multiple clock periods, the period count is set by the reference multi-period count registers - lower 16 bits: r0mpcrl, r1mpcrl, r2mpcrl and r3mpcrl and the reference multi-period count registers - upper 16 bits: r0 mpcru, r1mpcru, r2mpcru, and r3mpcru. the near upper measurement limits are set by the mult i-period near upper limit registers, mpnulrl and mpnulru. the far upper measurement limits are set by the mu lti-period far upper limit registers, mpfulrl and mpfulru. the near lower measurement limits are set by the mu lti-period near lower limi t registers, mpnllrl and mpnllru. the far lower measurement limits are set by the multi- period far lower limit registers, mpfllrl and mpfllru. the registers? default values upon the device reset comply to stratum 3 when reference frequencies are 8 khz. if mrle (bit 2) of the dpll control register (dpllcr) is not set, all above mentioned regi sters for limits and counter values will be ignored and the stratum 3 default values wi ll be used. the values that comply to stratum 3 for each reference frequency upper limit (in 10 ns units) lower limit (in 10 ns units) comment 8 khz ?h2e4a ?h335c 6.4 us (10 uip-p of 1.544 mhz) 1.544 mhz ?h002b ?h0055 0.3 uip-p 2.048 mhz ?h0025 ?h003b 0.2 uip-p 4.096 mhz ?h0011 ?h001e 0.2 uip-p 8.192 mhz ?h0007 ?h000f 0.2 uip-p 16.384 mhz ?h0002 ?h0008 0.2 uip-p 19.44 mhz ?h0002 ?h0007 0.2 uip-p table 12 - default values for single period limits
zl50018 data sheet 47 zarlink semiconductor inc. detected input reference frequency are used. in order to use programmed valu es for the monitor registers, mrle (bit 2) has to be set, in the eventuality that val ues other than stratum 3 compliant values are desired. 16.0 microprocessor port the device provides access to the internal regi sters, connection memories and data memories via the microprocessor port. the microprocessor port is capable of supporting both motorola and intel non-multiplexed microprocessors. the microproces sor port consists of a 16-bit parallel data bus (d15 - 0), 14 bit address bus (a13 - 0) and six control signals (mot_intel , cs , ds _rd , r/w _wr , irq and dta _rdy). the data memory can only be read from the microprocessor port. for a data memory read operation, d7 - 0 will be used and d15 - 8 will output zeros. for a cm_l read or write oper ation, all bits (d15 - 0) of the data bus will be used. for a cm_h write operation, d4 - 0 of the data bus must be configured and d15 - 5 are ignored. d15 - 5 must be driven either high or low. for a cm_h read operation, d4 - 0 will be used and d15 - 5 will output zeros. refer to figure 26 on page 108, figure 27 on page 109, figure 28 on page 110 and figure 29 on page 111 for the microprocessor timing. 17.0 device reset and initialization the reset pin is used to reset the zl50018. when this pin is low, the following functions are performed: ? synchronously puts the microprocessor port in a reset state ? tristates the stio0 - 31 outputs ? drives the stohz0 - 15 outputs to high ? preloads all internal registers with their default values (refer to the individual registers for default values) ? clears all internal counters 17.1 power-up sequence the recommended power-up sequence is for the v dd_io supply (normally +3.3 v) to be established before the power-up of the v dd_core supply (normally +1.8 v). the v dd_core supply may be powered up at the same time as v dd_io , but should not ?lead? the v dd_io supply by more than 0.3 v. stratum 3 default values (in 10 ns units) far upper limit -11.287 ppm ?h3b9a9de8 near upper limit -9.913 ppm ?h3b9aa346 nominal value 0ppm ?h3b9ac9ff near lower limit 9.913 ppm ?h3b9af0b8 far lower limit 11.287 ppm ?h3b9af616 table 13 - default multi-period hysteresis limits
zl50018 data sheet 48 zarlink semiconductor inc. 17.2 device initialization on reset upon power up, the zl50018 should be initialized as follows: ? set the ode pin to low to disable the stio0 - 31 outputs and to drive stohz0 - 15 to high ? set the trst pin to low to disable the jtag tap controller ? reset the device by pulsing the reset pin to zero for longer than 1 s ? after releasing the reset pin from low to high, wait for a certain period of time (see note below) for the device to stabilize from the power down state before the first microprocessor port access can occur ? program ckin1 - 0 (bit 6 -5) in the control register (cr) to define the frequency of the cki and fpi inputs ? wait at least 500 s prior to the next microport access (see note below) ? use the block programming mode to initialize the connection memory ? release the ode pin from low to high after the connection memory is programmed note: if an external oscillator is used, the waiting time is 500 s. without the external oscillator, if cki is 16.384 mhz, the waiting time is 500 s; if cki is 8.192 mhz, the waiting time is 1ms; if cki is 4.096 mhz, the waiting time is 2 ms. 17.3 software reset in addition to the hardware reset from the reset pin, the device can also be reset by using software reset. there are two software reset bits in the software reset register (srr). srstdpll (bit 0) is used to reset the dpll while srstsw (bit 1) resets the rest of the switch. 18.0 pseudo-random bit generation and error detection the zl50018 has one bit error rate (ber) transmitter and one ber receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receiver s associated with the input streams. each transmitter can generate a ber sequence with a pattern of 2 15 -1 pseudo-random code (itu o.151). each transmitter can start at any loca tion on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 s). the ber receivers and transmitters are enabled by programming the rberen (bit 5) and tberen (bit 4) in the ims register. in order to save power, the 32 transmitters and/or receivers can be disabled. (this is the default state.) multiple connection memory locations can be programme d for ber tests such that the ber patterns can be transmitted for multiple consecutive output channels. if consecutive input channel s are not selected, the ber receiver will not compar e the bit patterns corr ectly. the number of ou tput channels which t he ber pattern occupies has to be the same as the number of channels defined in the ber length register (brlr) which defines how many ber channels are to be monitored by the ber receiver. for each input stream, there is a set of register s for the ber test. the registers are as follows: ? ber receiver control register ( brcr ) - st[n]cber (bit 1) is used to clear the bit receiver error register (brer). st[n]sber (bit 0) is used to enable the per-stream ber receiver. ? ber receiver start register ( brsr ) - st[n]brs7 - 0 (bit 7 - 0) defines the input channel from which the ber sequence will start to be compared. ? ber receiver length register ( brlr ) - st[n]bl8 - 0 (bit 8 - 0) define how many channels the sequence will last. depending on the data rate being used, the ber test can last for a maximum of 32, 64, 128 or 256 channels at the data rates of 2.048, 4.096, 8.192 or 16 .384 mbps, respectively. the minimum length of the ber test is a single channel. the user must take care to program the correct channel length for the ber test so that the channel length does not exceed the to tal number of channels available in the stream.
zl50018 data sheet 49 zarlink semiconductor inc. ? ber receiver error register ( brer ) - this read-only register contains the number of counted errors. when the error count reaches 0xffff, the ber counter will st op updating so that it will not overflow. st[n]cber (bit 1) in the ber receiver control register is used to reset the brer register. for normal ber operation, cmm (bit 0) must be 1 in the connection memory low (cm_l). pcc1 - 0 (bits 2 - 1) in the connection memory low must be programmed to ?10? to enable the per-stream based ber transmitters. for each stream, the length (or total number of channels) of ber testing can be as long as one whole frame, but the channels must be consecutive. upon completion of pr ogramming the connection memory, the corresponding ber receiver can be started by setting st[n ]sber (bit 0) in the brcr to high. there must be at least 2 frames (250 s) between completion of connection memory programming and starting the ber receiver before the ber receiver can correctly identify ber errors. a 16 bit ber counter is used to count the number of bit errors. 19.0 pcm a-law/ -law translation the zl50018 provides per-channel code translation to be used to adapt pulse code modulation (pcm) voice or data traffic between networks which us e different encoding laws. code translation is valid in both connection mode and message mode. in order to use this feature, t he connection memory high (cm_h) ent ry for the output channel must be programmed. v /d (bit 4) defines if the traffic in the channel is voice or data. setting icl1 - 0 (bits 3 - 2) programs the input coding law and ocl1 - 0 (bits 1- 0) programs the output coding law as shown in table 14. the different code options are: for voice coding options, the it u-t g.711 a-law and itu-t g.711 -law are the standard rules for encoding. a-law without alternate bit inversion (abi) is an alternative code that does not invert the even bits (6, 4, 2, 0). -law without magnitude inversion (mi) is an al ternative code that does not perform in version of magnitude bits (6, 5, 4, 3, 2, 1, 0). when transferring data code, the option ?no code? does not invert the bits. th e alternate bit inversion (abi) option inverts the even bits (6, 4, 2, 0) while the inverted alternat e bit inversion (abi) inverts the odd bits (7, 5, 3, 1). when the ?all bits inverted? option is selected, all of th e bits (7, 6, 5, 4, 3, 2, 1, 0) are inverted. the input channel and output channel encoding law are configured independent ly. if the output channel coding is set to be different from the input c hannel, the zl50018 performs translation between the two standards. if the input and output encoding laws are set to the same standard, no translation occurs. as the v /d (bit 4) of the connection memory high (cm_h) must be set on a per-channel basis, it is not possible to translate between voice and data encoding laws. input coding (icl1- 0) output coding (ocl1 - 0) voice coding (v /d bit = 0) data coding (v /d bit = 1) 00 00 itu-t g.711 a-law no code 01 01 itu-t g.711 -law alternate bit inversion (abi) 10 10 a-law without alternate bit inversion (abi) inverted alternate bit inversion (abi) 11 11 -law without magnitude inversion (mi) all bits inverted table 14 - input and output voice and data coding
zl50018 data sheet 50 zarlink semiconductor inc. 20.0 quadrant frame programming by programming the stream input quadr ant frame registers (siqfr0 - 31), users can divide one frame of input data into four quadrant frames and can force the lsb or msb of every input channel in these quadrants to one or zero for robbed-bit signaling. the four quadrant frames are defined as follows: when the quadrant frame control bits, stin[n]q3c2 - 0 (bit 11 - 9), stin[n]q2c2 - 0 (bit 8 - 6), stin[n]q1c2 - 0 (bit 5 - 3) or stin[n]q1c2 - 0 (bit 2 - 0), are set, the lsb or msb of every input channel in t he quadrant is forced to ?1? or ?0? as shown by the following table: note that quadrant frame programming and ber recept ion cannot be used simultaneously on the same input stream. 21.0 jtag port the jtag test port is implemented to meet the mandat ory requirements of the ieee -1149.1 (jtag) standard. the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. 21.1 test access port (tap) the test access port (tap) accesses the zl50018 test func tions. it consists of three input pins and one output pin as follows: ? test clock input (tck) - tck provides the clock for the test logic. tck does not interfere with any on-chip clock and thus remains independent in the functional mode. tck permits shifting of test data into or out of the boundary-scan register cells concurrently with t he operation of the device and without interfering with the on-chip logic. ? test mode selection inputs (tms) - the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to high when it is not driven from an external source. data rate quadrant 0 quadrant 1 quadrant 2 quadrant 3 2.048 mbps channel 0 - 7 channel 8 - 15 channel 16 - 23 channel 24 - 31 4.096 mbps channel 0 - 15 channel 16 - 31 channel 32 - 47 channel 48 - 63 8.192 mbps channel 0 - 31 channel 32 - 63 channel 64 - 95 channel 96 - 127 16.384 mbps channel 0 - 63 channel 64 - 127 channel 128 - 191 channel 192 - 255 table 15 - definition of the four quadrant frames stin[n]q[y]c[2:0] action 0xx normal operation 100 replaces lsb of every channel in quadrant y with ?0? 101 replaces lsb of every channel in quadrant y with ?1? 110 replaces msb of every channel in quadrant y with ?0? 111 replaces msb of every channel in quadrant y with ?1? note: y = 0, 1, 2, 3 table 16 - quadrant frame bit replacement
zl50018 data sheet 51 zarlink semiconductor inc. ? test data input (tdi) - serial input data applied to this port is fed ei ther into the instruction register or into a test data register, depending on the sequence previous ly applied to the tms input. the registers are described in a subsequent section. the received input data is sampled at the rising edge of the tck pulse. this pin is internally pulled to high when it is not driven from an external source. ? test data output (tdo) - depending on the sequence previously applied to the tms input, the contents of either the instruction register or test data register are serially shif ted out towards tdo. the data from tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) - resets the jtag scan structure. this pin is internally pulled to high when it is not driven from an external source. 21.2 instruction register the zl50018 uses the public instructions defined in the ieee-1149.1 standard. the jtag interface contains a four-bit instruction register. instructi ons are serially loaded into the instruct ion register from the tdi when the tap controller is in its shifted-or state. these instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the in struction is current and to define the serial test data register path that is used to shift data between tdi and tdo during data register scanning. 21.3 test data registers as specified in the ieee-1149.1 standard, the zl50018 jtag inte rface contains three test data registers: ? the boundary-scan register - the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the z l50018 core logic. ? the bypass register - the bypass register is a single stage shift register that provides a one-bit path from tdi to tdo. ? the device identification register - the jtag device id for the zl50018 is 0c36214b h 21.4 bsdl a boundary scan description language (bsdl) file is availabl e from zarlink semiconductor to aid in the use of the ieee-1149.1 test interface. version <31:28> 0000 part number <27:12> 1100 0011 0110 0010 manufacturer id <11:1> 0001 0100 101 lsb <0> 1
zl50018 data sheet 52 zarlink semiconductor inc. 22.0 register address mapping address a13 - a0 cpu access register name abbreviation reset by 0000 h r/w control register cr switch/hardware 0001 h r/w internal mode selection register ims switch/hardware 0002 h r/w software reset register srr hardware only 0003 h r/w output clock and frame pulse control register ocfcr dpll/hardware 0004 h r/w output clock and frame pulse selection register ocfsr dpll/hardware 0005 h r/w fpo_off0 register fpoff0 dpll/hardware 0006 h r/w fpo_off1 register fpoff1 dpll/hardware 0007 h r/w fpo_off2 register fpoff2 dpll/hardware 0010 h r only internal flag register ifr switch/hardware 0011 h r only ber error flag register 0 berfr0 switch/hardware 0012 h r only ber error flag register 1 berfr1 switch/hardware 0013 h r only ber receiver lock register 0 berlr0 switch/hardware 0014 h r only ber receiver lock register 1 berlr1 switch/hardware 0040 h r/w dpll control register dpllcr dpll/hardware 0041 h r/w reference frequency register rfr dpll/hardware 0042 h r/w centre frequency register - lower 16 bits cfrl dpll/hardware 0043 h r/w centre frequency register - upper 10 bits cfru dpll/hardware 0044 h r/w software delta frequency register swdfr dpll/hardware 0045 h r only frequency offset register for dpll/hardware 0046 h r/w frequency locking range register flrr dpll/hardware 0047 h r/w lock detector threshold register ldtr dpll/hardware 0048 h r/w lock detector interval register ldir dpll/hardware 0049 h r/w slew rate limit register srlr dpll/hardware 004a h r/w bandwidth control register bwcr dpll/hardware 004b h r/w reference change control register rccr dpll/hardware 004c h r only reference change status register rcsr dpll/hardware 004e h r/w multi-period near upper limit register - lower 16 bits mpnulrl dpll/hardware table 17 - address map for registers (a13 = 0)
zl50018 data sheet 53 zarlink semiconductor inc. 004f h r/w multi-period near upper limit register - upper 16 bits mpnulru dpll/hardware 0050 h r/w multi-period far upper limit register - lower 16 bits mpfulrl dpll/hardware 0051 h r/w multi-period far upper limit register - upper 16 bits mpfulru dpll/hardware 0052 h r/w multi-period near lower limit regist er - lower 16 bits mpnllrl dpll/hardware 0053 h r/w multi-period near lower limit regist er - upper 16 bits mpnllru dpll/hardware 0054 h r/w multi-period far lower limit register - lower 16 bits mpfllrl dpll/hardware 0055 h r/w multi-period far lower limit register - upper 16 bits mpfllru dpll/hardware 0056 h r/w reference 0 multi-period count regi ster - lower 16 bits r0mpcrl dpll/hardware 0057 h r/w reference 0 multi-period count regi ster - upper 16 bits r0mpcru dpll/hardware 0058 h r/w reference 0 upper limit register r0ulr dpll/hardware 0059 h r/w reference 0 lower limit register r0llr dpll/hardware 005a h r/w reference 1 multi-period count regi ster - lower 16 bits r1mpcrl dpll/hardware 005b h r/w reference 1 multi-period count regi ster - upper 16 bits r1mpcru dpll/hardware 005c h r/w reference 1 upper limit register r1ulr dpll/hardware 005d h r/w reference 1 lower limit register r1llr dpll/hardware 005e h r/w reference 2 multi-period count regi ster - lower 16 bits r2mpcrl dpll/hardware 005f h r/w reference 2 multi-period count regi ster - upper 16 bits r2mpcru dpll/hardware 0060 h r/w reference 2 upper limit register r2ulr dpll/hardware 0061 h r/w reference 2 lower limit register r2llr dpll/hardware 0062 h r/w reference 3 multi-period count regi ster - lower 16 bits r3mpcrl dpll/hardware 0063 h r/w reference 3 multi-period count regi ster - upper 16 bits r3mpcru dpll/hardware 0064 h r/w reference 3 upper limit register r3ulr dpll/hardware 0065 h r/w reference 3 lower limit register r3llr dpll/hardware 0066 h r only interrupt register ir dpll/hardware 0067 h r/w interrupt mask register imr dpll/hardware 0068 h r/w interrupt clear r egister icr dpll/hardware 0069 h r only reference status register rsr dpll/hardware 006a h r/w reference mask register rmr dpll/hardware 006b h r only reference frequency status register rfsr dpll/hardware 006c h r/w output jitter control register ojcr dpll/hardware 0100 h - 011f h r/w stream input control registers 0 - 31 sicr0 - 31 switch/hardware table 17 - address map for registers (a13 = 0) (continued)
zl50018 data sheet 54 zarlink semiconductor inc. 0120 h - 013f h r/w stream input quadrant frame register s 0 - 31 siqfr0 - 31 switch/hardware 0200 h - 021f h r/w stream output control register s 0 - 31 socr0 - 31 switch/hardware 0300 h - 031f h r/w ber receiver start registers 0 - 31 brsr0 - 31 switch/hardware 0320 h - 033f h r/w ber receiver length registers 0 - 31 brlr0 - 31 switch/hardware 0340 h - 035f h r/w ber receiver control registers 0 - 31 brcr0 - 31 switch/hardware 0360 h - 037f h r only ber receiver error registers 0 - 31 brer0 - 31 switch/hardware table 17 - address map for registers (a13 = 0) (continued)
zl50018 data sheet 55 zarlink semiconductor inc. 23.0 detailed register description bit name description 15 - 14 unused reserved. in normal functional mode, these bits must be set to zero. 13 slv_ dpllen dpll enable in slave mode (ignored in master mode) when this bit is low, dpll is disabled in slave mode. when this bit is high and osc_en = 1, the dpll is enabled in slave mode. when slv_dpllen is set in slave mode, ck o[3:0] and fpo[3:0] are generated from cki and fpi. cko[5:4] and fpo[5] are lock ed to the selected input reference (one of ref[3:0]). in this mode of operation, the dpll retains its functionality, including the generation of the ref_fail[3:0] output si gnals. see table 7, ?zl50018 operating modes? on page 37 for more details. 12 - 11 opm1 - 0 operation mode these bits are used to set the device in master/slave operation. refer to table 7, ?zl50018 operating modes? on page 37 for more details. 10 cki_lp cki and fpi loopback (ignored in slave mode) when this bit is low, cki and fpi are used as input pins. when this bit is high, cki and fpi are internally looped back from cko2 (16.384 mhz) and fpo2 respectively, and cki pin and fpi pin should be tied low or high externally; ckin1 - 0 (bits 6 - 5) of this register should be programmed to be 00. see table 7, ?zl50018 operating modes? on page 37 for more details. 9fpinpos input frame pulse (fpi) position when this bit is low, fpi straddles frame boundary (as defined by st-bus). when this bit is high, fpi starts from frame boundary (as defined by gci-bus) 8ckinp clock input (cki) polarity when this bit is low, the cki falling edge aligns with the frame boundary. when this bit is high, the cki risi ng edge aligns with the frame boundary. 7fpinp frame pulse input (fpi) polarity when this bit is low, the input frame puls e fpi has the negative frame pulse format. when this bit is high, the input frame pulse fpi has the positive frame pulse format. 6 - 5 ckin1 - 0 input clock (cki) and fram e pulse (fpi) selection the mode_4m0 and mode_4m1 pins, as described in ?pin description? on page 13, should also be set to define the input clock mode. table 18 - control register (cr) bits external read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 slv_ dpllen opm 1 opm 0 cki_ lp fpin pos ckinp fpinp ckin 1 ckin 0 var en mbpe osb ms1 ms0 ckin1 - 0 fpi active period cki 00 61 ns 16.384 mhz 01 122 ns 8.192 mhz 10 244 ns 4.096 mhz 11 reserved
zl50018 data sheet 56 zarlink semiconductor inc. 4 varen variable delay mode enable when this bit is low, the variable delay mode is disabled on a device-wide basis. when this bit is high, the variable delay mode is enabled on a device-wide basis. 3 mbpe memory block programming enable when this bit is high, the connection me mory block programming mode is enabled to program the connection memory. when it is low, the memory block programming mode is disabled. 2osb output stand by bit this bit enables the stio0 - 31 and the stohz0 -15 serial outputs. the following table describes the hiz control of the serial data outputs: note: unused output streams are tristated (s tio = hiz, stohz = driven high). refer to socr0 - 31 (bit2 - 0). 1 - 0 ms1 - 0 memory select bits these two bits are used to select connection memory low, connec- tion high or data memory for access by cpu: bit name description table 18 - control register (cr) bits (continued) external read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 slv_ dpllen opm 1 opm 0 cki_ lp fpin pos ckinp fpinp ckin 1 ckin 0 var en mbpe osb ms1 ms0 reset pin srstsw (in srr) ode pin osb bit stio0 - 31 stohz0 - 15 0 x x x hiz driven high 1 1 x x hiz driven high 1 0 0 x hiz driven high 1 0 1 0 hiz driven high 1011 active (controlled by cm) active (controlled by cm) ms1 - 0 memory selection 00 connection memory low read/write 01 connection memory high read/write 10 data memory read 11 reserved
zl50018 data sheet 57 zarlink semiconductor inc. bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8stio_pd_ en stio pull-down enable when this bit is low, the pull-down re sistors on all stio pads will be disabled. when this bit is high, t he pull-down resistors on all stio pads will be enabled. 7bdh bi-directional contro l for streams 16-31 6bdl bi-directional contro l for streams 0-15 5 rberen prbs receiver enable when this bit is low, all the ber receiver s are disabled. to enable any ber receivers, this bit must be high. 4 tberen prbs transmitter enable when this bit is low, all the ber transmitters are disabled. to enable any ber transmitters, this bit must be high. 3 - 1 bpd2 - 0 block programming data these bits refer to the value to be loaded into the connec- tion memory, whenever the memory block pr ogramming feature is activated. after the mbpe bit in the control register is set to hi gh and the mbps bit in th is register is set to high, the contents of the bits bpd2 - 0 are loaded into bits 2 - 0 of the connection memory low. bits 15 - 3 of the connection memory low and bits 15 - 0 of connection memory high are zeroed. table 19 - internal mode selection register (ims) bits external read/write address: 0001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000stio_ pd_en bdh bdl rber en tber en bpd 2 bpd 1 bpd 0 mbps bdh stio16 - 31 operation 0 normal operation: sti16-31 are inputs stio16-31 are outputs 1 bi-directional operation: sti16-31 tied low internally stio16-31 are bi-directional bdl stio0 - 15 operation 0 normal operation: sti0-15 are inputs stio0-15 are outputs 1 bi-directional operation: sti0-15 tied low internally stio0-15 are bi-directional
zl50018 data sheet 58 zarlink semiconductor inc. 0 mbps memory block programming start a zero to one transition of this bit starts the memory block progr amming function. the mbps and bpd2 - 0 bits in this register mu st be defined in the same write operation. once the mbpe bit in the control register is set to high, the device requires two frames to complete the block programmin g. after the programmi ng function has fin- ished, the mbps bit returns to low, indicating the operation is completed. when mbps is high, mbps or mbpe can be set to low to abort the pr ogramming operation. whenever the microprocessor writes a one to the mbps bit, the block programming function is started. as long as this bit is hi gh, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. bit name description 15 - 2 unused reserved. in normal functional mode, these bits must be set to zero. 1srstsw software reset bit for switch when this bit is low, data switching blocks are in normal operation. when this bit is high, data switching blocks are in software reset state. refer to table 17, ?address map for registers (a13 = 0)? on page 52 for details regarding which registers are affected. 0srstdpll software reset bit for dpll when this bit is low, the dpll block is in normal operation. when this bit is high, the dpll block is in software reset state. refer to table 17, ?address map for registers (a13 = 0)? on page 52 for details regarding which registers are affected. table 20 - software reset register (srr) bits bit name description table 19 - internal mode selection register (ims) bits (continued) external read/write address: 0001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000stio_ pd_en bdh bdl rber en tber en bpd 2 bpd 1 bpd 0 mbps external read/write address: 0002 h reset value: 0000 h 15141312111098765432 1 0 00000000000000srst sw srst dpll
zl50018 data sheet 59 zarlink semiconductor inc. bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8 fpof2en fpo_off2/fpo5 enable when this bit is high, output frame pulse fpo_off2/fpo5 is enabled. when this bit is low, output frame pulse fpo_off2/fpo5 is in high impedance state. 7 fpof1en fpo_off1 enable when this bit is high, output frame pulse fpo_off1 is enabled. when this bit is low, output frame pulse fpo_off1 is in high impedance state. 6 fpof0en fpo_off0 enable when this bit is high, output frame pulse fpo_off0 is enabled. when this bit is low, output frame pulse fpo_off0 is in high impedance state. 5cko5en cko5 enable when this bit is high, output clock cko5 is enabled. when this bit is low, output clock cko5 is in high impedance state. cko5 is available in master mode or in slave mode with slv_dpllen set. 4cko4en cko4 enable when this bit is high, output clock cko4 is enabled. when this bit is low, output clock cko4 is in high impedance state. cko4 is available in master mode or in slave mode with slv_dpllen set. 3ckofpo3 en cko3 and fpo3 enable when this bit is high, output clock cko3 and output frame pulse fpo3 are enabled. when this bit is low, cko3 and fpo3 are in high impedance state. 2ckofpo2 en cko2 and fpo2 enable when this bit is high, output clock cko2 and output frame pulse fpo2 are enabled. when this bit is low, cko2 and fpo2 are in high impedance state. 1ckofpo1 en cko1 and fpo1 enable when this bit is high, output clock cko1 and output frame pulse fpo1 are enabled. when this bit is low, cko1 and fpo1 are in high impedance state. 0ckofpo0 en cko0 and fpo0 enable when this bit is high, output clock cko0 and output frame pulse fpo0 are enabled. when this bit is low, cko0 and fpo0 are in high impedance state. table 21 - output clock and frame pulse control register (ocfcr) bits external read/write address: 0003 h reset value: 0000 h 1514131211109 8 7 6 5 4 3210 0000000fpof2 en fpof1 en fpof0 en cko5 en cko4 en cko fpo3 en cko fpo2 en cko fpo1 en cko fpo0 en
zl50018 data sheet 60 zarlink semiconductor inc. bit name description 15 cko4p output clock (cko4) polarity selection when this bit is low, the output clock cko4 falling edge aligns with the frame boundary. when this bit is high, the output clock cko4 rising edge aligns with the frame boundary. cko4 is available in master mode or in slave mode with slv_dpllen set. 14 cko4sel output clock (cko4) frequency selection when this bit is low, the output clock cko4 is 2.048 mhz. when this bit is high, the output clock cko4 is 1.544 mhz. cko4 is available in master mode or in slave mode with slv_dpllen set. 13 - 12 ckofpo3 sel1 - 0 output clock (cko3) frequency and ou tput frame pulse (fpo3) pulse cycle selection 11 cko3p output clock (cko3) polarity selection when this bit is low, the output clock cko3 falling edge aligns with the frame boundary. when this bit is high, the output clock cko3 rising edge aligns with the frame boundary. 10 fpo3p output frame pulse (fpo3) polarity selection when this bit is low, the output frame pul se fpo3 has the negative frame pulse format. when this bit is high, the output frame pul se fpo3 has the positive frame pulse format. 9fpo3pos output frame pulse (fpo3) position when this bit is low, fpo3 straddles frame boundary (as defined by st-bus). when this bit is high, fpo3 starts from frame boundary (as defined by gci-bus). 8cko2p output clock (cko2) polarity selection when this bit is low, the output clock cko2 falling edge aligns with the frame boundary. when this bit is high, the output clock cko2 rising edge aligns with the frame boundary. 7fpo2p output frame pulse (fpo2) polarity selection when this bit is low, the output frame pul se fpo2 has the negative frame pulse format. when this bit is high, the output frame pul se fpo2 has the positive frame pulse format. table 22 - output clock and frame pu lse selection register (ocfsr) bits external read/write address: 0004 h reset value: 0000 h 1514131211109876543210 cko4 p cko4 sel cko fpo3 sel1 cko fpo3 sel0 cko3 p fpo3 p fpo3 pos cko2 p fpo2 p fpo2 pos cko1 p fpo1 p fpo1 pos cko0 p fpo0 p fpo0 pos ckofpo3 sel1 - 0 fpo3 cko3 00 244 ns 4.096 mhz 01 122 ns 8.192 mhz 10 61 ns 16.384 mhz 11 30 ns 32.768 mhz
zl50018 data sheet 61 zarlink semiconductor inc. 6fpo2pos output frame pulse (fpo2) position when this bit is low, fpo2 straddles frame boundary (as defined by st-bus). when this bit is high, fpo2 starts from frame boundary (as defined by gci-bus). 5cko1p output clock (cko1) polarity selection when this bit is low, the output clock cko1 falling edge aligns with the frame boundary. when this bit is high, the output clock cko1 rising edge aligns with the frame boundary. 4fpo1p output frame pulse (fpo1) polarity selection when this bit is low, the output frame pul se fpo1 has the negative frame pulse format. when this bit is high, the output frame pul se fpo1 has the positive frame pulse format. 3fpo1pos output frame pulse (fpo1) position when this bit is low, fpo1 straddles frame boundary (as defined by st-bus). when this bit is high, fpo1 starts from frame boundary (as defined by gci-bus). 2cko0p output clock (cko0) polarity selection when this bit is low, the output clock cko0 falling edge aligns with the frame boundary. when this bit is high, the output clock cko0 rising edge aligns with the frame boundary. 1fpo0p output frame pulse (fpo0) polarity selection when this bit is low, the output frame pul se fpo0 has the negative frame pulse format. when this bit is high, the output frame pul se fpo0 has the positive frame pulse format. 0fpo0pos output frame pulse (fpo0) position when this bit is low, fpo0 straddles frame boundary (as defined by st-bus). when this bit is high, fpo0 starts from frame boundary (as defined by gci-bus). note: in divided slave modes, cko3 - 1 cannot exceed frequency of cki. cko[5:4] are available in master mode or in slave mode with slv_dpllen set. bit name description table 22 - output clock and frame pulse se lection register (ocfsr) bits (continued) external read/write address: 0004 h reset value: 0000 h 1514131211109876543210 cko4 p cko4 sel cko fpo3 sel1 cko fpo3 sel0 cko3 p fpo3 p fpo3 pos cko2 p fpo2 p fpo2 pos cko1 p fpo1 p fpo1 pos cko0 p fpo0 p fpo0 pos
zl50018 data sheet 62 zarlink semiconductor inc. bit name description 15 - 11 unused reserved. in normal functional mode, these bits must be set to zero. 10 fp19en 19.44mhz frame pulse output enable. (for fpo_off2 only) this bit is a reserved bit for fpo_off0 and fpo_off1, and must be set to zero. when this bit is high, fpo_off2 is negat ive frame pulse output corresponding to 19.44mhz without channel offset. when this bit is low, fpo_off2 is out put frame pulse with channel offset. 9 - 2 fof[n]off7 - 0 fpo_off[n] channel offset the binary value of these bits refers to the channel offset from original frame bound- ary. permitted channel offset values depend on bits 1-0 of this register. 1 - 0 fof[n]c1 - 0 fpo_off[n] control bits. note: [n] denotes output offset frame pulse from 0 to 2. table 23 - fpo_off[n] register (fpo_off[n]) bits external read/write address: 0005 h - 0007 h reset value: 0000 h 1514131211109876543210 00000fp19 en fof[n] off7 fof[n] off6 fof[n] off5 fof[n] off4 fof[n] off3 fof[n] off2 fof[n] off1 fof[n] off0 fof[n] c1 fof[n] c0 fof[n]c 1-0 data rate (mbps) fpo_off[n] pulse cycle width fof[n]off7 - 0 permitted channel offset polarity control position control 00 2.048 one 4.096 mhz clock 0 - 31 fpo0p fpo0pos 01 4.096 one 8.192 mhz clock 0 - 63 fpo1p fpo1pos 10 8.192 one 16.384 mhz clock 0 - 127 fpo2p fpo2pos 11 16.384 one 16.384 mhz clock 0 - 255 fpo2p fpo2pos
zl50018 data sheet 63 zarlink semiconductor inc. bit name description 15 - 2 unused reserved in normal functional mode, these bits are zero. 1outerr output error (read only) this bit is set high when the total num ber of output channels is programmed to be more than the maximum capacity of 2048, in which case the output channels beyond the maximum capacity should be disabled. this bit will be cleared automatica lly after programming is corrected. 0inerr input error (read only) this bit is set high when the total number of input channels is programmed to be more than the maximum capacity of 2048, in which case the input channels beyond the maximum capacity should be di sabled.this bit will be clea red automatically after pro- gramming is corrected. table 24 - internal flag register (ifr) bits - read only bit name description 15 - 0 berf[n] ber error flag[n]: if berf[n] is high, it indicates that ber receiver error register [n] (brer[n]) is not zero. if berf[n] is low, it indicates that ber re ceiver error register [n] (brer[n]) is zero. note: [n] denotes input stream from 0 - 15. table 25 - ber error flag register 0 (berfr0) bits - read only external read address: 0010 h reset value: 0000 h 15141312111098765432 1 0 00000000000000out err in err external read address: 00011 h reset value: 0000 h 1514131211109876543210 ber f15 ber f14 ber f13 ber f12 ber f11 ber f10 ber f9 ber f8 ber f7 ber f6 ber f5 ber f4 ber f3 ber f2 ber f1 ber f0
zl50018 data sheet 64 zarlink semiconductor inc. bit name description 15 - 0 berf[n] ber error flag[n] if berf[n] is high, it indicates that ber receiver error register [n] (brer[n]) is not zero. if berf[n] is low, it indicates that ber re ceiver error register [n] (brer[n]) is zero. note: [n] denotes input stream from 16 - 31. table 26 - ber error flag register 1 (berfr1) bits - read only bit name description 15 - 0 berl[n] ber receiver lock[n] if berl[n] is high, it indicates that ber receiver of sti[n] is locked. if berl[n] is low, it indicates that ber receiver of sti[n] is not locked. note: [n] denotes input stream from 0 - 15. table 27 - ber receiver lock register 0 (berlr0) bits - read only external read/write address: 00012 h reset value: 0000 h 1514131211109876543210 ber f31 ber f30 ber f29 ber f28 ber f27 ber f26 ber f25 ber f24 ber f23 ber f22 ber f21 ber f20 ber f19 ber f18 ber f17 ber f16 external read address: 00013 h reset value: 0000 h 1514131211109876543210 ber l15 ber l14 ber l13 ber l12 ber l11 ber l10 ber l9 ber l8 ber l7 ber l6 ber l5 ber l4 ber l3 ber l2 ber l1 ber l0
zl50018 data sheet 65 zarlink semiconductor inc. bit name description 15 - 0 berl[n] ber receiver lock[n] if berl[n] is high, it indicates that ber receiver of sti[n] is locked. if berl[n] is low, it indicates that ber receiver of sti[n] is not locked. note: [n] denotes input stream from 16 - 31. table 28 - ber receiver lock register 1 (berlr1) bits - read only bit name description 15-8 unused reserved. in normal functional mode, these bits must be set to zero. 7lin_res linear response of dpll phase multiplier. when this bit is high, linear phase multiplication will be used to determine the jitte r transfer characterist ics. (follow the jitter transfer as per bwcr register for small and large jitter amplitude). when this bit is low, non-linear phase multip lication will be used to determine the jitter transfer characteristics. (only high jitter am plitudes follow the jitter transfer as per bwcr register). when 0, dpll has bett er holdover stabilit y and output jitter. 6sm_fst semi-fast locking control bit. when this bit is high, the semi-fast locking mode is enabled, allowing the fast frequency lock ( ffl3 - 0) bits in the bwcr register to be used even if the dpll slew rate limiter is not bypassed. when this bit is low, the ffl3 - 0 bits in the bwcr register are ignored if the bypass limiter bit (blm) in the bwcr register is not set. 5 unused reserved. in normal functional mode, this bit must be set to zero. table 29 - dpll control register (dpllcr) bits external read address: 00014 h reset value: 0000 h 1514131211109876543210 ber l31 ber l30 ber l29 ber l28 ber l27 ber l26 ber l25 ber l24 ber l23 ber l22 ber l21 ber l20 ber l19 ber l18 ber l17 ber l16 external read/write address: 0040 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000lin_ res sm_ fst 0 swf swe mrle rfre dpll _irm
zl50018 data sheet 66 zarlink semiconductor inc. 4swf software mode fast control bit. when this bit is low, the swe bit is high, and the dpll is in freerun mode (the fdm1 - 0 bits of the rccr register are =?11?), the software slow control mode is enabled. the dpll outputs will stabiliz e to delta frequency contents of software delta frequency register (swd fr), after programmed internal dpll filter response and phase alignment speed (phase slope) time. when this bit is high, the swe bit is high, and the dpll is in freerun mode, the software fast control mode is enabled . the dpll outputs will reach the delta frequency contents of software delta frequency register (swd fr), immediately after writing to the software delta frequency register, therefore allowing external software filters and phase alignment speed (phase slope) limiters to be used. this case will usually require very frequent updating of the swdfr register. when the swe bit is low or the dpll is not in freerun mode, this bit is ignored. 3swe software mode enable bit. when this bit is low, the software delta frequency register (swdfr) content is ignored and the software mode of the dpll is disabled. when this bit is high and the dpll is in freerun m ode, the dpll software mode is enabled, meaning that the software delta frequency regi ster content is used to control the dpll output frequency, depending on the valu e of swf bit of this register. when the dpll is not in freerun mode, this bit is ignored. 2mrle monitor register limits enable bit. when this bit is low, t he monitor register content is ignored and the stratum 3 default value for each detected reference frequency is used to set up the dpll?s reference monitoring func tions. when this bit is high, the monitor registers contents are used to control the monitoring functionalit y of the device. the following registers are affected: rnulr, rnllr, rnmpcrl, rnmpcru, mpnulrl, mpnulru, mpfulrl, mpfulru, mpnllrl, mpnllru, mpfllrl, mpfllru. 1rfre reference frequency register enable. when this bit is low, the reference frequency value used in the dpll comes from appropriate reference frequency detector. when this bit is high, the reference frequency val ue comes from reference frequency register (rfr). 0 dpll_ irm dpll internal reset mode. when this bit is low, the dpll module is in the operational state. when this bit is high, the dpll module is in the power saving mode. registers are not reset and are still accessible in the power saving mode. bit name description table 29 - dpll control register (dpllcr) bits (continued) external read/write address: 0040 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00000000lin_ res sm_ fst 0 swf swe mrle rfre dpll _irm
zl50018 data sheet 67 zarlink semiconductor inc. bit name description 15-12 unused reserved in normal functional mode, these bits must be set to zero. 11 - 9 r3f2 - 0 reference 3 frequency bits when the rfre bit of the dpll cr register is high, these bi ts are used to select the ref3 input frequency. when the rfre bit is low, these bits are ignored. 8 - 6 r2f2 - 0 reference 2 frequency bits when the rfre bit of the dpll cr register is high, these bi ts are used to select the ref2 input frequency. when the rfre bit is low, these bits are ignored. table 30 - reference frequency register (rfr) bits external read/write address: 0041 h reset value: 0000 h 1514131211109876543210 0 0 0 0 r3f2r3f1r3f0r2f2r2f1r2f0r1f2r1f1r1f0r0f2r0f1r0f0 r3f2 r3f1 r3f0 ref 3 input frequency 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 101 16.384mhz 110 19.44mhz 111 reserved r2f2 r2f1 r2f0 ref 2 input frequency 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 101 16.384mhz 110 19.44mhz 111 reserved
zl50018 data sheet 68 zarlink semiconductor inc. 5 - 3 r1f2 - 0 reference 1 frequency bits when the rfre bit of the dpll cr register is high, these bi ts are used to select the ref1 input frequency. when the rfre bit is low, these bits are ignored. 2 - 0 r0f2 - 0 reference 0 frequency bits when the rfre bit of the dpll cr register is high, these bi ts are used to select the ref0 input frequency. when the rfre bit is low, these bits are ignored. bit name description table 30 - reference frequency register (rfr) bits (continued) external read/write address: 0041 h reset value: 0000 h 1514131211109876543210 0 0 0 0 r3f2r3f1r3f0r2f2r2f1r2f0r1f2r1f1r1f0r0f2r0f1r0f0 r1f2 r1f1 r1f0 ref 1 input frequency 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 101 16.384mhz 110 19.44mhz 111 reserved r0f2 r0f1 r0f0 ref 0 input frequency 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 101 16.384mhz 110 19.44mhz 111 reserved
zl50018 data sheet 69 zarlink semiconductor inc. bit name description 15 - 0 cfn15 - 0 center frequency number (cfn) lower 16 bits: the total binary value of these bits and the cfru register bits defi nes the output center frequency number according to the following formula: where, f out is desired output center frequency, while f mclk is frequency of dpll master clock. for given master clock frequency of 100mhz, and desired output center frequency of 65.536mhz, the cfn has the value of: the register contents should be changed only if compensation fo r input oscillator (or crystal) frequency offset is required. e.g. if master clock frequency is off by + 20 ppm (100.002 mhz -> 5 times multiplied c20i of 20.0004 mhz), the cfn should be programmed to be: the default value of this register should not be changed in any other circumstances. table 31 - centre frequency register - lower 16 bits (cfrl) external read/write address: 0042 h reset value: 16b1 h 1514131211109876543210 cfn 15 cfn 14 cfn 13 cfn 12 cfn 11 cfn 10 cfn 9 cfn 8 cfn 7 cfn 6 cfn 5 cfn 4 cfn 3 cfn 2 cfn 1 cfn 0 f out cfn 2 26 ----------- - f mclk = cfn 2 26 65.536mhz 100mhz ------------------------------- 2 26 0.65536 43980465 29f16b1 h ==== cfn 2 26 65.536mhz 100.002mhz ---------------------------------- - 2 26 0.65534689 43979585 29f1341 h ====
zl50018 data sheet 70 zarlink semiconductor inc. bit name description 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9 - 0 cfn25 - 16 center frequency number (cfn) upper 10 bits the total binary value of these bits and the cf rl register bits repr esents the center fre- quency number (cfn) explained under cfrl register bits explanation. the default value of this register should be changed only if compensation for input oscil- lator (or crystal) frequency offset is required, and should not be changed in any other circumstances. table 32 - centre frequency register - upper 10 bits (cfru) bit name description 15 unused reserved. in normal functional mode, this bit must be set to zero. 14 - 0 sdf14 - 0 software delta frequency bits: when the swe bit in the dpllcr register is high and the dpll is in freerun mode (the fdm1-0 bits of the rccr register are =?11?), the binary value of these bits represents the ta rgeted deviation of the dpll output from its center frequency (delta frequency). depending on the swf bit in the dpllcr register, the deviation will be met immediately or after programmed filter response and phase alignment speed (phase slope) time. when t he swe bit in the dpllcr register is low or the dpll is not in freer un mode, these bits are ignored. defined in same units as cfn in the 2's complement format. note: note: examples of programming: if +10 ppm is desired output frequency, the sdf14-0 should be: cfn x 0.00001 = 440 = 01b8 h if -10 ppm is desired output frequency, the sdf14-0 should be: cfn x (-0.00001) = -440 = 7e48 h table 33 - software delta frequency register (swdfr) bits external read/write address: 0043 h reset value: 029f h 1514131211109876543210 000000cfn 25 cfn 24 cfn 23 cfn 22 cfn 21 cfn 20 cfn 19 cfn 18 cfn 17 cfn 16 external read/write address: 0044 h reset value: 0000 h 1514131211109876543210 0sdf 14 sdf 13 sdf 12 sdf 11 sdf 10 sdf 9 sdf 8 sdf 7 sdf 6 sdf 5 sdf 4 sdf 3 sdf 2 sdf 1 sdf 0
zl50018 data sheet 71 zarlink semiconductor inc. bit name description 15 unused reserved. in normal functional mode, this bit is zero. 14 - 0 fof14 - 0 frequency offset bits: the binary value of these bits represents the current deviation of the dpll output from its center frequenc y. defined in same units as cfn in the 2's complement format. in the software fast mode these bits do not represent frequency offset since the internal filter and phase alignment speed (phase slope) limiter are not used. note: note 1: output frequency offset, relative to master clock, will be represented as the following: +10 ppm: cfn x 0.00001 = 440 = 01b8 h -10 ppm: cfn x (-0.00001) = -440 = 7e48 h table 34 - frequency offset register (for) bits - read only bit name description 15 - 14 unused reserved. in normal functional mode, these bits must be set to zero. 13 - 0 flr13 - 0 frequency lock range bits: if not in the limiter bypass mo de, the binary value of these bits defines the maximum allow ed deviation of the dpll output from its center frequency. if the dpll limiter bypass is set in the bandwidth control register, the dpll output fre- quency can exceed the value specified by these bits, since the proportional value of ref- erence-to-feedback difference is predominant to the integration value in that case. defined in same units as cfn (unsigned). note: the default value is 20 ppm (?h0370/cfn = 20 ppm). table 35 - frequency locking range register (flrr) bits external read only address: 0045 h 1514131211109876543210 0fof 14 fof 13 fof 12 fof 11 fof 10 fof 9 fof 8 fof 7 fof 6 fof 5 fof 4 fof 3 fof 2 fof 1 fof 0 external read/write address: 0046 h reset value: 0370 h (see note) 1514131211109876543210 00flr 13 flr 12 flr 11 flr 10 flr 9 flr 8 flr 7 flr 6 flr 5 flr 4 flr 3 flr 2 flr 1 flr 0
zl50018 data sheet 72 zarlink semiconductor inc. bit name description 15 - 0 ldt15 - 0 lock detect threshold bits the binary value of these bits defines th e upper limit of the absolute phase from the phase detector output for lock detection. when the value of the absolute phase is less than or equal to ldt for duration of time defined by the ldir register, the dpll locks. when the value of the absolute phase is greater than ldt for duration of time defined by the ldir register divided by 256, the dpll does not lock. note: ldt should be calculated as per the maximum ex pected amplitude of jitter on the active input reference using the following formula: ldt = max_exp_jitter ( ns ) x 2 15.2 (ns) example: if maximum expected jitter amplitude on 2.048 mhz reference is 10ui (i.e., 10 x 488. ns = 4882 ns) (assuming the jitter frequency where dpll attenuation is big), the ldt shou ld be programmed to be (4882/15.2) x 2 = 642 = 0282 h table 36 - lock detector threshold register (ldtr) bits bit name description 15 - 0 ldi15 - 0 lock detector interval bits the binary value of these bits defines the time interval t hat the output phase detector must be below the lock detect threshold to declare lock. unsigned representation of the ldi bits is defined in 4 ms intervals. table 37 - lock detector interval register (ldir) bits external read/write address: 0047 h reset value: 000f h 1514131211109876543210 ldt 15 ldt 14 ldt 13 ldt 12 ldt 11 ldt 10 ldt 9 ldt 8 ldt 7 ldt 6 ldt 5 ldt 4 ldt 3 ldt 2 ldt 1 ldt 0 external read/write address: 0048 h reset value: 2c00 h 1514131211109876543210 ldi 15 ldi 14 ldi 13 ldi 12 ldi 11 ldi 10 ldi 9 ldi 8 ldi 7 ldi 6 ldi 5 ldi 4 ldi 3 ldi 2 ldi 1 ldi 0
zl50018 data sheet 73 zarlink semiconductor inc. bit name description 15 - 13 unused reserved. in normal functional mode, these bits must be set to zero. 12 - 0 srl12 - 0 slew rate limit bits: the binary value of these bits defines the maximum rate of dpll phase change (phase slope), where the phase represents difference between the input reference and output feedback clock. defined in same units as cfn (unsigned). note: the default value is 56 ppm (?h099f/cfn = 56 ppm). table 38 - slew rate limit register (srlr) bits bit name description 15 - 14 unused reserved. in normal functional mode, these bits must be set to zero. 13 blm bypass limiter bit: when this bit is high, the dpll slew rate limiter is bypassed (ignored). in combination with flf_qs, flc3 - 0, ffl3 - 0 and lpf3 - 0 bits, causes fast locking of the dpll output clocks to the selected reference. when this bit is low, the dpll performs nor mal lock following the slew rate limit defined in the slew rate limit register (srlr). 12 flf_qs fast lock frequency quick stabilization bit: this bit is used to control speed of internal frequenc y stabilization. when this bit is high, the dpll internal freque ncy will quickly stabilize to the appropriate value, allowing very fast storage of holdover frequency value. when this bit is low, the internal frequency value will be reached over normal locking time (i.e. <100 seconds), and some extra jitter on output clocks can be expected. it is recommended to set this bit if fast locking functionality is desired. when the blm bit is low, this bit is ignored. 11 - 8 flc3 - 0 fast lock control bits: value of these bits (unsigned) control stability of frequency when ffl3 - 0 bits of this register are used. larger values result in faster locking and are recommended for reference clocks with sm all jitter, while smaller values are recommended for references with presence of significant jitter. table 39 - bandwidth cont rol register (bwcr) bits external read/write address: 0049 h reset value: 099f h (see note) 1514131211109876543210 000srl 12 srl 11 srl 10 srl 9 srl 8 srl 7 srl 6 srl 5 srl 4 srl 3 srl 2 srl 1 srl 0 external read/write address: 004a h reset value: 0002 h (see note) 1514131211109876543210 00blmflf_ qs flc 3 flc 2 flc 1 flc 0 ffl 3 ffl 2 ffl 1 ffl 0 lpf 3 lpf 2 lpf 1 lpf 0
zl50018 data sheet 74 zarlink semiconductor inc. 7 - 4 ffl3 - 0 fast frequency lock bits: when the blm bit in this register is high or when sm_fst bit in the dpllcr register is high, value of these bits (uns igned) represents fast locking speed of the dpll output clocks to the acti ve input reference. the value also represents speed grade that internal frequency value, us ed in holdover mode, reaches the dpll output frequency. the bigger the value, the faster the locking. when both the blm and the sm_fst bits are low, these bits are ignored. 3 - 0 lpf3 - 0 low pass filter control bits: define the dpll low pass filter corner frequency. note 1: the default corner frequency (-3 db point) of the low pass filter is 1.9 hz. note 2: to set fast lock mode, it is recommended to program the register bits as follows: lpf3-0 ->?h8, unless a specific filter response (low pass filter characteristic) is required ffl3-0 ->?hf flc3-0 ->?hf, if significant amount of jitter is not present on the active reference input flf_qs -> 1 blm -> 1 note 3: in fast lock mode, it is important that the device is not also in freerun mode (see the rccr register). otherwise, the output frame pulse may not be generated correctly. note 4: if the selected reference is 8 khz, lpf3 - 0 should not be chosen to have corner frequency higher than 1/10 of the carri er frequency, or 800hz (i.e. bits lpf3 - 0 should have a value equal to or smaller than 1010). note 5: when the ffl3 - 0 bits are used in normal locking mode (when the blm bit is not set and the sm_fst bit in the dpllcr register is set), the dpll locking time increases as the unsigned binary representation of ffl3 - 0 value increases, maintaining given phase alignment speed (phase slope). the dpll peaking, which is limited by some standards, increases as well, so the ffl3 - 0 must be chosen with respect to given standard requirements. bit name description table 39 - bandwidth control register (bwcr) bits (continued) external read/write address: 004a h reset value: 0002 h (see note) 1514131211109876543210 00blmflf_ qs flc 3 flc 2 flc 1 flc 0 ffl 3 ffl 2 ffl 1 ffl 0 lpf 3 lpf 2 lpf 1 lpf 0 lpf3 lpf2 lpf1 lpf0 corner frequency of dpll filter 0 0 0 0 0.47 hz 0 0 0 1 0.95 hz 0 0 1 0 1.9 hz 0 0 1 1 3.8 hz 0 1 0 0 7.6 hz 0 1 0 1 15.2 hz 0 1 1 0 30.4 hz 0 1 1 1 60.7 hz 1 0 0 0 121 hz 1 0 0 1 243 hz 1 0 1 0 486 hz 1 0 1 1 971 hz 1 1 0 0 1.94 khz 1 1 0 1 3.88 khz 1 1 1 0 7.77 khz 111 1 15.54khz
zl50018 data sheet 75 zarlink semiconductor inc. bit name description 15 - 8 unused reserved. in normal functional mode, these bits must be set to zero. 7mtr mtie reset: when this bit is low, the mtie circuit applies a phase offset between the reference input clock and the dpll outp ut clock and the phase offset value is maintained. when this bit is high, mtie circuit is in its reset state and the phase offset value is reset to zero, causing alignment of the dpll output clocks to nearest edge of the selected input reference. 6 - 5 prs1 - 0 preferred reference selection bits: these bits select the preferred reference from one of the input references. they are used only if the pms2-0 bits are set to 001. otherwise, these bits are ignored. 4 - 2 pms2 - 0 preference mode selection bits: these bits select one of the preference modes: if in automatic mode with a preferred reference (pms2-0 = 001 and fdm1-0 = 00), the automatic state machine will only switch between two references (as per table 8). please see section 12.1.3.2, ?automatic reference switching with preference? on page 40 for more details. table 40 - reference change control register (rccr) bits external read/write address: 004b h reset value: 0000 h 1514131211109876543210 00000000mtrprs 1 prs 0 pms 2 pms 1 pms 0 fdm 1 fdm 0 prs1 prs0 preferred reference selection 00 ref0 01 ref1 10 ref2 11 ref3 pms2 pms1 pms0 preference mode 0 0 0 no preference 0 0 1 preference as per the setting of the prs1 - 0 bits 0 1 0 force ref0 0 1 1 force ref1 1 0 0 force ref2 1 0 1 force ref3 110 - 111 reserved
zl50018 data sheet 76 zarlink semiconductor inc. 1 - 0 fdm1 - 0 force dpll timing mode: these bits force the dpll into one of the valid timing modes. in freerun mode, it is important that the dp ll is not also in fast lock mode (see the bwcr register). otherwise, the output frame pulses may not be generated correctly. bit name description 15 - 9 unused reserved. in normal functional mode, these bits are zero. 8slm slew rate limiter status bit: if the device sets this bit to high, the dpll phase difference between the input and output clocks is changing at the slew rate limit defined in the slew rate limit register (srlr). 7lst lock status bit: if the device sets this bit to high, while the ldtr and ldir registers are programmed properly, the dpll output clocks are locked to the selected input reference. if this bit is low, the dpll output clocks ar e not yet locked to the selected input reference. table 41 - reference change status register (rcsr) bits - read only bit name description table 40 - reference change control register (rccr) bits (continued) external read/write address: 004b h reset value: 0000 h 1514131211109876543210 00000000mtrprs 1 prs 0 pms 2 pms 1 pms 0 fdm 1 fdm 0 fdm1 fdm0 dpll timing mode 00 automatic 01 normal 1 0 holdover 11 freerun external read only address: 004c h 151413121110987654321 0 0 0 0 0 0 0 0 slm lst rfr2 rfr1 rfr0 res1 res0 dpm1 dpm0
zl50018 data sheet 77 zarlink semiconductor inc. 6 - 4 rfr2 - 0 reference frequency indicator bits: these bits represent the frequency of the selected reference indicated by the reference bits (res1 - 0) in this register. 3 - 2 res1 - 0 reference select indicator bits: these bits indicate which one of the four reference inputs (ref0 - 3 pins) is being selected by the device. 1 - 0 dpm1 - 0 dpll timing mode status bits: these bits indicate the dpll?s timing mode status. bit name description table 41 - reference change status register (rcsr) bits - read only (continued) external read only address: 004c h 151413121110987654321 0 0 0 0 0 0 0 0 slm lst rfr2 rfr1 rfr0 res1 res0 dpm1 dpm0 rfr2 rfr1 rfr0 frequency of the selected reference 0 0 0 8 khz 001 1.544 mhz 010 2.048 mhz 011 4.096 mhz 100 8.192 mhz 1 0 1 16.384 mhz 1 1 0 19.44 mhz 1 1 1 reserved res1 res0 input reference in use 00 ref 0 01 ref 1 10 ref 2 11 ref 3 dpm1 dpm0 dpll timing mode state 00 mtie 01 normal 1 0 holdover 1 1 freerun
zl50018 data sheet 78 zarlink semiconductor inc. bit name description 15 - 0 mnu15 - 0 multiple-period near upper limit bits: total binary value of these bits and the mpnulru register bits defines the near upper limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents near upper limit for all reference frequencies, which is +9.913 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?upper? is based on frequency. table 42 - multi-period near upper limit register - lower 16 bits (mpnulrl) bit name description 15 - 0 mnu31 - 16 multiple-period near upper limit bits: total binary value of these bits and the mpnulrl register bits defines the near u pper limit for the mult iple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents near upper limit for all reference frequencies, which is +9.913 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?upper? is based on frequency. table 43 - multi-period near upper limit register - upper 16 bits (mpnulru) external read/write address: 004e h reset value: a346 h (note 1) 1514131211109876543210 mnu 15 mnu 14 mnu 13 mnu 12 mnu 11 mnu 10 mnu 9 mnu 8 mnu 7 mnu 6 mnu 5 mnu 4 mnu 3 mnu 2 mnu 1 mnu 0 external read/write address: 004f h reset value: 3b9a h (note 1) 1514131211109876543210 mnu 31 mnu 30 mnu 29 mnu 28 mnu 27 mnu 26 mnu 25 mnu 24 mnu 23 mnu 22 mnu 21 mnu 20 mnu 19 mnu 18 mnu 17 mnu 16
zl50018 data sheet 79 zarlink semiconductor inc. bit name description 15 - 0 mfu15 - 0 multiple-period far upper limit bits: total binary value of these bits and the mpfulru register bits defines the far upper limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents far upper limit for all reference frequencies, which is +11.287 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?upper? is based on frequency. table 44 - multi-period far upper limit register - lower 16 bits (mpfulrl) bit name description 15 - 0 mfu31 - 16 multiple-period far upper limit bits: total binary value of these bits and the mpfulrl register bits defines the far upper limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents far upper limit for all reference frequencies, which is +11.287 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?upper? is based on frequency. table 45 - multi-period far upper limit register - upper 16 bits (mpfulru) external read/write address: 0050 h reset value: 9de8 h (note 1) 1514131211109876543210 mfu 15 mfu 14 mfu 13 mfu 12 mfu 11 mfu 10 mfu 9 mfu 8 mfu 7 mfu 6 mfu 5 mfu 4 mfu 3 mfu 2 mfu 1 mfu 0 external read/write address: 0051 h reset value: 3b9a h (note 1) 1514131211109876543210 mfu 31 mfu 30 mfu 29 mfu 28 mfu 27 mfu 26 mfu 25 mfu 24 mfu 23 mfu 22 mfu 21 mfu 20 mfu 19 mfu 18 mfu 17 mfu 16
zl50018 data sheet 80 zarlink semiconductor inc. bit name description 15 - 0 mnl15 - 0 multiple-period near lower limit bits: total binary value of these bits and the mpnllru register bits defines the near lower limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents near lower limit for all reference frequencies, which is -9.913 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?lower? is based on frequency. table 46 - multi-period near lower limit register - lower 16 bits (mpnllrl) bit name description 15 - 0 mnl31 - 16 multiple-period near lower limit bits: total binary value of these bits and the mpnllrl register bits defines the near lo wer limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents near lower limit for all reference frequencies, which is -9.913 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?lower? is based on frequency. table 47 - multi-period near lower limit register - upper 16 bits (mpnllru) external read/write address: 0052 h reset value:f0b8 h (note 1) 1514131211109876543210 mnl 15 mnl 14 mnl 13 mnl 12 mnl 11 mnl 10 mnl 9 mnl 8 mnl 7 mnl 6 mnl 5 mnl 4 mnl 3 mnl 2 mnl 1 mnl 0 external read/write address: 0053 h reset value: 3b9a h (note 1) 1514131211109876543210 mnl 31 mnl 30 mnl 29 mnl 28 mnl 27 mnl 26 mnl 25 mnl 24 mnl 23 mnl 22 mnl 21 mnl 20 mnl 19 mnl 18 mnl 17 mnl 16
zl50018 data sheet 81 zarlink semiconductor inc. bit name description 15 - 0 mfl15 - 0 multiple-period far lower limit bits: total binary value of these bits and the mpfllru register bits defines the far lower limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents far lower limit for all reference frequencies, which is -11.287 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?lower? is based on frequency. table 48 - multi-period far lower limit register - lower 16 bits (mpfllrl) bit name description 15 - 0 mfl31 - 16 multiple-period far lower limit bits: total binary value of these bits and the mpfllrl register bits defines the far lower limit for the multiple period count of any reference input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents far lower limit for all reference frequencies, which is -11.287 ppm (stratum 3 compliant value), regardless of the reference frequency. note 2: the name ?lower? is based on frequency. table 49 - multi-period far lower li mit register - upper 16 bits (mpfllru) external read/write address: 0054 h reset value: f616 h (note 1) 1514131211109876543210 mfl 15 mfl 14 mfl 13 mfl 12 mfl 11 mfl 10 mfl 9 mfl 8 mfl 7 mfl 6 mfl 5 mfl 4 mfl 3 mfl 2 mfl 1 mfl 0 external read/write address: 0055 h reset value: 3b9a h (note 1) 1514131211109876543210 mfl 31 mfl 30 mfl 29 mfl 28 mfl 27 mfl 26 mfl 25 mfl 24 mfl 23 mfl 22 mfl 21 mfl 20 mfl 19 mfl 18 mfl 17 mfl 16
zl50018 data sheet 82 zarlink semiconductor inc. bit name description 15 - 0 mc[n]15 - 0 (n = 0 - 3) reference n multi-period count bits: total binary value of these bits and the rnmpcru register bits define s the number of reference clock periods to be measured for the multi-period frequency check for the refn input monitoring, minus 1 . note 1: the default value represents lower bits of multi-period count for 8khz input frequency, calculated to have 10 seconds observation time. note 2: when the mrle bit of dpllcr register is low, these registers are ignored. depending on reference frequency (detected or programmed through the reference frequency register), the following values are used instead: ?h387f - if reference frequency is 8 khz ?h987f - if reference frequency is 1.544 mhz ?h7fff - if reference frequency is 2.048 mhz ?hffff - if reference frequency is 4.096 mhz, 8.192 mhz or 16.384 mhz ?h4eff - if reference frequency is 19.44 mhz table 50 - multi-period count register - lower 16 bits (rnmpcrl) bits, (n = 0 - 3) external read/write addresses: 0056 h , 005a h , 005e h , 0062 h reset value: 387f h (see note 1) 1514131211109876543210 mc[n] 15 mc[n] 14 mc[n] 13 mc[n] 12 mc[n] 11 mc[n] 10 mc[n] 9 mc[n] 8 mc[n] 7 mc[n] 6 mc[n] 5 mc[n] 4 mc[n] 3 mc[n] 2 mc[n] 1 mc[n] 0
zl50018 data sheet 83 zarlink semiconductor inc. bit name description 15 - 0 mc[n]31 - 16 (n = 0 - 3) reference n multi-period count bits: total binary value of these bits and the rnmpcrl register bits defi nes the number of reference clock periods to be measured for the multi-period frequency check for the refn input monitoring, minus 1 . note 1: the default value represents lower bits of multi-period count for 8 khz input frequency, calculated to have 10 seconds observation time. note 2: when the mrle bit of dpllcr register is low, these registers are ignored. depending on reference frequency (detected or programmed through the reference frequency register), the following values are used instead: ?h0001 - if reference frequency is 8 khz ?h00eb - if reference frequency is 1.544 mhz ?h0138 - if reference frequency is 2.048 mhz ?h0270 - if reference frequency is 4.096 mhz ?h04e1 - if reference frequency is 8.192 mhz ?h09c3 - if reference frequency is 16.384 mhz ?h0b96 - if reference frequency is 19.44 mhz table 51 - multi-period count register - upper 16 bits (rnmpcru) bits, (n = 0 - 3) external read/write addresses: 0057 h , 005b h , 005f h , 0063 h reset value: 0001 h (see note 1) 1514131211109876543210 mc[n] 31 mc[n] 30 mc[n] 29 mc[n] 28 mc[n] 27 mc[n] 26 mc[n] 25 mc[n] 24 mc[n] 23 mc[n] 22 mc[n] 21 mc[n] 20 mc[n] 19 mc[n] 18 mc[n] 17 mc[n] 16
zl50018 data sheet 84 zarlink semiconductor inc. bit name description 15 - 0 ul[n]15 - 0 (n = 0 - 3) reference n single period upper limit bits: the binary value of these bits defines the upper limit for the period of the refn input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents limit for 8 khz input frequency, which is +6.4 s (+10 u i p-p of 1.544 mhz). note 2: when the mrle bit of dpllcr register is low, these registers are ignored. depending on reference frequency (detected or programmed through the reference frequency register), the following values are used instead: ?h2e4a (10uip-p of 1.544 mhz i.e. 6.4 s) - if reference frequency is 8 khz ?h002b (0.3uip-p) - if reference frequency is 1.544 mhz ?h0025 (0.2uip-p) - if reference frequency is 2.048 mhz ?h0011 (0.2uip-p) - if reference frequency is 4.096 mhz ?h0007 (0.2uip-p) - if reference frequency is 8.192 mhz ?h0002 (0.2uip-p) - if reference frequency is 16.384 mhz ?h0002 (0.2uip-p) - if reference frequency is 19.44 mhz note 3: the name ?upper? is based on frequency. table 52 - upper limit register (rnulr) bits, (n = 0 - 3) external read/write addresses: 0058 h , 005c h , 0060 h , 0064 h reset value: 2e4a h (see note 1) 1514131211109876543210 ul[n] 15 ul[n] 14 ul[n] 13 ul[n] 12 ul[n] 11 ul[n] 10 ul[n] 9 ul[n] 8 ul[n] 7 ul[n] 6 ul[n] 5 ul[n] 4 ul[n] 3 ul[n] 2 ul[n] 1 ul[n] 0
zl50018 data sheet 85 zarlink semiconductor inc. bit name description 15 - 0 ll[n]15 - 0 (n = 0 to 3) reference n single period lower limit bits: the binary value of these bits defines the lower limit for the period of the refn input, minus 1 . the unit of the binary value is measured in 100 mhz clock periods. note 1: the default value represents limit for 8 khz input frequency, which is -6.4 s (-10 ui p-p of 1.544 mhz). note 2: when the mrle bit of dpllcr register is low, these registers are ignored. depending on reference frequency (detected or programmed through the reference frequency register), the following values are used instead: ?h335c (10uip-p of 1.544 mhz i.e. 6.4 s) - if reference frequency is 8 khz ?h0055 (0.3uip-p) - if reference frequency is 1.544 mhz ?h003b (0.2uip-p) - if reference frequency is 2.048 mhz ?h001e (0.2uip-p) - if reference frequency is 4.096 mhz ?h000f (0.2uip-p) - if reference frequency is 8.192 mhz ?h0008 (0.2uip-p) - if reference frequency is 16.384 mhz ?h0007 (0.2uip-p) - if reference frequency is 19.44 mhz note 3: the name ?lower? is based on frequency. table 53 - lower limit register (rnllr) bits, (n = 0 - 3) external read/write addresses: 0059 h , 005d h , 0061 h , 0065 h reset value: 335c h (see note 1) 1514131211109876543210 ll[n] 15 ll[n] 14 ll[n] 13 ll[n] 12 ll[n] 11 ll[n] 10 ll[n] 9 ll[n] 8 ll[n] 7 ll[n] 6 ll[n] 5 ll[n] 4 ll[n] 3 ll[n] 2 ll[n] 1 ll[n] 0
zl50018 data sheet 86 zarlink semiconductor inc. bit name description 15 - 4 unused reserved. in normal functional mode, these bits is zero. 3lci lock change interrupt bit: if the device sets this bit to high, the device lock status has changed. 2 rci reference change interrupt bit: if the device sets this bit to high, the selected reference has changed. 1hoi holdover interrupt bit: if the device sets this bit to high, the device has entered or recovered from the holdover/mtie mode. 0sli slew rate limit interrupt bit: if the device sets this bit to high, the device phase status has changed from perspective of changing at the slew rate limit. note 1: if any of these bits are set, the interrupt output will bec ome active unless the interrupt mask register (imr) has a hig h value for that particular bit. note 2: any of these bits can be cleared by setting the appropriate bit in the interrupt clear register. table 54 - interrupt register (ir) bits - read only external read only address: 0066 h 1514131211109876543210 000000000000lcircihoisli
zl50018 data sheet 87 zarlink semiconductor inc. bit name description 15 - 4 unused reserved. in normal functional mode, these bits must be set to zero. 3lim lock interrupt mask bit: when this bit is high, it masks the lock status change interrupt. 2rim reference change interrupt mask bit: when this bit is high, it masks the reference change interrupt. 1him holdover interrupt mask bit: when this bit is high, it masks the holdover entry/exit interrupt. 0sim slew rate limiter interrupt mask bit: when this bit is high, it masks the slew rate interrupt. table 55 - interrupt mask register (imr) bits bit name description 15 - 4 unused reserved. in normal functional mode, these bits must be set to zero. 3 - 0 icb3 - 0 interrupt clear bits: writing a ?1? to any bit in th is register will clear the corresponding bit in the interrupt register (ir). the interrupt clear register is self-clearing, i.e., once it has completed it s action, the icr register bit returns to 0. table 56 - interrupt clear register (icr) bits external read/write address: 0067 h reset value: 000f h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000000limrimhimsim external read/write address: 0068 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000000000000icb 3 icb 2 icb 1 icb 0
zl50018 data sheet 88 zarlink semiconductor inc. bit name description 15 r3fml reference 3 multi-period lower limit fail bit: if the device sets this bit to high, the input ref3 fails the multi-period lower limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 14 r3fmu reference 3 multi-period upper limit fail bit: if the device sets this bit to high, the input ref3 fails the multi-period upper limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 13 r3fl reference 3 single period lower limit fail bit: if the device sets this bit to high, the input ref3 fails the single-period lowe r limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 12 r3fu reference 3 single period upper limit fail bit: if the device sets this bit to high, the input ref3 fails the single-period upper limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 11 r2fml reference 2 multi-period lower limit fail bit: if the device sets this bit to high, the input ref2 fails the multi-period lower limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 10 r2fmu reference 2 multi-period upper limit fail bit: if the device sets this bit to high, the input ref2 fails the multi-period upper limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 9r2fl reference 2 single period lower limit fail bit: if the device sets this bit to high, the input ref2 fails the single-period lower limi t check. (see table 11, ?values for single period limits? on page 45) 8r2fu reference 2 single period upper limit fail bit: if the device sets this bit to high, the input ref2 fails the single-period upper limit check. (see table 11, ?values for single period limits? on page 45) 7r1fml reference 1 multi-period lower limit fail bit: if the device sets this bit to high, the input ref1 fails the multi-period lower limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 6r1fmu reference 1 multi-period upper limit fail bit: if the device sets this bit to high, the input ref1 fails the multi-period upper limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 5r1fl reference 1 single period lower limit fail bit: if the device sets this bit to high, the input ref1 fails the single-period lower limi t check. (see table 11, ?values for single period limits? on page 45) table 57 - reference failure status register (rsr) bits - read only external read only address: 0069 h 1514131211109876543210 r3 fml r3 fmu r3 fl r3 fu r2 fml r2 fmu r2 fl r2 fu r1 fml r1 fmu r1 fl r1 fu r0 fml r0 fmu r0 fl r0 fu
zl50018 data sheet 89 zarlink semiconductor inc. 4r1fu reference 1 single period upper limit fail bit: if the device sets this bit to high, the input ref1 fails the single-period upper limit check. (see table 11, ?values for single period limits? on page 45) 3r0fml reference 0 multi-period lower limit fail bit: if the device sets this bit to high, the input ref0 fails the multi-period lower limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 2r0fmu reference 0 multi-period upper limit fail bit: if the device sets this bit to high, the input ref0 fails the multi-period upper limit check. (see table 13, ?default multi-period hysteresis limits? on page 47) 1r0fl reference 0 single period lower limit fail bit: if the device sets this bit to high, the input ref0 fails the single-period lower limi t check. (see table 11, ?values for single period limits? on page 45) 0r0fu reference 0 single period upper limit fail bit: if the device sets this bit to high, the input ref0 fails the single-period upper limit check. (see table 11, ?values for single period limits? on page 45) bit name description 15 r3mml reference 3 multi-period lower limit mask bit: when this bit is high, it masks the multi-period lower limit check (or forces pass) for ref3. 14 r3mmu reference 3 multi-period upper limit mask bit: when this bit is high, it masks the multi-period upper limit check (or forces pass) for ref3. 13 r3ml reference 3 single-period lower limit mask bit: when this bit is high, it masks the single-period lower limit check (or forces pass) for ref3. 12 r3mu reference 3 single-period upper limit mask bit: when this bit is high, it masks the single-period upper limit check (or forces pass) for ref3. table 58 - reference mask register (rmr) bits bit name description table 57 - reference failure status register (rsr) bits - read only (continued) external read only address: 0069 h 1514131211109876543210 r3 fml r3 fmu r3 fl r3 fu r2 fml r2 fmu r2 fl r2 fu r1 fml r1 fmu r1 fl r1 fu r0 fml r0 fmu r0 fl r0 fu external read/write address: 006a h reset value: 0000 h 1514131211109876543210 r3 mml r3 mmu r3 ml r3 mu r2 mml r2 mmu r2 ml r2 mu r1 mml r1 mmu r1 ml r1 mu r0 mml r0 mmu r0 ml r0 mu
zl50018 data sheet 90 zarlink semiconductor inc. 11 r2mml reference 2 multi-period lower limit mask bit: when this bit is high, it masks the multi-period lower limit check (or forces pass) for ref2. 10 r2mmu reference 2 multi-period upper limit mask bit: when this bit is high, it masks the multi-period upper limit check (or forces pass) for ref2. 9r2ml reference 2 single-period lower limit mask bit: when this bit is high, it masks the single-period lower limit check (or forces pass) for ref2. 8r2mu reference 2 single-period upper limit mask bit: when this bit is high, it masks the single-period upper limit check (or forces pass) for ref2. 7 r1mml reference 1 multi-period lower limit mask bit: when this bit is high, it masks the multi-period lower limit check (or forces pass) for ref1. 6 r1mmu reference 1 multi-period upper limit mask bit: when this bit is high, it masks the multi-period upper limit check (or forces pass) for ref1. 5r1ml reference 1 single-period lower limit mask bit: when this bit is high, it masks the single-period lower limit check (or forces pass) for ref1. 4r1mu reference 1 single-period upper limit mask bit: when this bit is high, it masks the single-period upper limit check (or forces pass) for ref1. 3 r0mml reference 0 multi-period lower limit mask bit: when this bit is high, it masks the multi-period lower limit check (or forces pass) for ref0. 2 r0mmu reference 0 multi-period upper limit mask bit: when this bit is high, it masks the multi-period upper limit check (or forces pass) for ref0. 1r0ml reference 0 single-period lower limit mask bit: when this bit is high, it masks the single-period lower limit check (or forces pass) for ref0. 0r0mu reference 0 single-period upper limit mask bit: when this bit is high, it masks the single-period upper limit check (or forces pass) for ref0. bit name description table 58 - reference mask register (rmr) bits (continued) external read/write address: 006a h reset value: 0000 h 1514131211109876543210 r3 mml r3 mmu r3 ml r3 mu r2 mml r2 mmu r2 ml r2 mu r1 mml r1 mmu r1 ml r1 mu r0 mml r0 mmu r0 ml r0 mu
zl50018 data sheet 91 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits are zero. 11 - 9 r3fs2 - 0 reference 3 frequency status bits: these bits report detected frequency of ref3. 8 - 6 r2fs2 - 0 reference 2 frequency status bits: these bits report detected frequency of ref2. table 59 - reference frequency status register (rfsr) bits - read only external read only address: 006b h 1514131211109876543210 0000r3fs 2 r3fs 1 r3fs 0 r2fs 2 r2fs 1 r2fs 0 r1fs 2 r1fs 1 r1fs 0 r0fs 2 r0fs 1 r0fs 0 r3fs2 r3fs1 r3fs0 ref3 frequency measurement 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 1 0 1 16.384 mhz 1 1 0 19.44 mhz 1 1 1 reserved r2fs2 r2fs1 r2fs0 ref2 frequency measurement 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 101 16.384mhz 1 1 0 19.44 mhz 1 1 1 reserved
zl50018 data sheet 92 zarlink semiconductor inc. 5 - 3 r1fs2 - 0 reference 1 frequency status bits: these bits report detected frequency of ref1. 2 - 0 r0fs2 - 0 reference 0 frequency status bits: these bits report detected frequency of ref0. bit name description table 59 - reference frequency status register (rfsr) bits - read only (continued) external read only address: 006b h 1514131211109876543210 0000r3fs 2 r3fs 1 r3fs 0 r2fs 2 r2fs 1 r2fs 0 r1fs 2 r1fs 1 r1fs 0 r0fs 2 r0fs 1 r0fs 0 r1fs2 r1fs1 r1fs0 ref1 frequency measurement 000 8khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 1 0 1 16.384 mhz 1 1 0 19.44 mhz 1 1 1 reserved r0fs2 r0fs1 r0fs0 ref0 frequency measurement 000 8 khz 0 0 1 1.544 mhz 0 1 0 2.048 mhz 0 1 1 4.096 mhz 1 0 0 8.192 mhz 1 0 1 16.384 mhz 1 1 0 19.44 mhz 1 1 1 reserved
zl50018 data sheet 93 zarlink semiconductor inc. bit name description 15 - 3 unused reserved. in normal functional mode, these bits must be set to zero. 2 - 0 ojp2 - 0 output jitter performance bits: these bits are used to control the dpll output jitter performance with respect to the noise re ceived through the output pins. the higher value (unsigned) means more filtering, while zero means filter bypass. the default value of 2 h gives the best performanc e for most circumstances. table 60 - output jitter control register (ojcr) bits bit name description 15 - 9 unused reserved . in normal functional mode, these bits must be set to zero . 8 - 6 stin[n]bd2 - 0 input stream[n] bit delay bits. the binary value of these bits refers to the number of bits that the input stream will be delayed relative to fpi. the maxi mum value is 7. zero means no delay. 5 - 4 stin[n]smp1 - 0 input data sampling point selection bits : table 61 - stream input control register 0 - 31 (sicr0 - 31) bits external read/write address: 006c h reset value: 0002 h 1514131211109876543210 0000000000000ojp2ojp1ojp0 external read/write address: 0100 h - 011f h reset value: 0000 h 1514131211109876543210 0000000stin[n] bd2 stin[n] bd1 stin[n] bd0 stin[n] smp1 stin[n] smp0 stin[n] dr3 stin[n] dr2 stin[n] dr1 stin[n] dr0 stin[n]smp1-0 sampling point (2.048 mbps, 4.096 mbps, 8.192 mbps streams) sampling point (16.384 mbps streams) 00 3/4 point 2/4 point 01 1/4 point 10 2/4 point 4/4 point 11 4/4 point
zl50018 data sheet 94 zarlink semiconductor inc. 3 - 0 stin[n]dr3 - 0 input data rate selection bits: note: [n] denotes input stream from 0 - 31. bit name description table 61 - stream input control register 0 - 31 (sicr0 - 31) bits (continued) external read/write address: 0100 h - 011f h reset value: 0000 h 1514131211109876543210 0000000stin[n] bd2 stin[n] bd1 stin[n] bd0 stin[n] smp1 stin[n] smp0 stin[n] dr3 stin[n] dr2 stin[n] dr1 stin[n] dr0 stin[n]dr3-0 data rate 0000 stream unused 0001 2.048 mbps 0010 4.096 mbps 0011 8.192 mbps 0100 16.384 mbps 0101 - 1111 reserved
zl50018 data sheet 95 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 - 9 stin[n]q3c2 - 0 quadrant frame 3 control bits. these three bits are used to control sti[n]?s quadrant frame 3, which is defined as ch24 to 31, ch48 to 63, ch96 to 127 and ch192 to 255 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. 8 - 6 stin[n]q2c2 - 0 quadrant frame 2 control bits. these three bits are used to control sti[n]?s quadrant frame 2, which is defined as ch16 to 23, ch32 to 47, ch64 to 95 and ch128 to 191 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. table 62 - stream input quadrant frame register 0 - 31 (siqfr0 - 31) bits external read/write address: 0120 h - 013f h reset value: 0000 h 1514131211109876543210 0000 stin[n] q3c2 stin[n] q3c1 stin[n] q3c0 stin[n] q2c2 stin[n] q2c1 stin[n] q2c0 stin[n] q1c2 stin[n] q1c1 stin[n] q1c0 stin[n] q0c2 stin[n] q0c1 stin[n] q0c0 stin[n]q3c 2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1? stin[n]q2c 2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1?
zl50018 data sheet 96 zarlink semiconductor inc. 5 - 3 stin[n]q1c2 - 0 quadrant frame 1 control bits. these three bits are used to control sti[n]?s quadrant frame 1, which is defined as ch8 to 15, ch16 to 31, ch32 to 63 and ch64 to 127 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. 2 - 0 stin[n]q0c2 - 0 quadrant frame 0 control bits. these three bits are used to control sti[n]?s quadrant frame 0, which is defined as ch0 to 7, ch0 to 15, ch0 to 31 and ch0 to 63 for the 2.048 mbps, 4.096 mbps, 8.192 mbps, and 16.384 mbps modes respectively. note: [n] denotes input stream from 0 - 31. bit name description table 62 - stream input quadrant frame regi ster 0 - 31 (siqfr0 - 31) bits (continued) external read/write address: 0120 h - 013f h reset value: 0000 h 1514131211109876543210 0000 stin[n] q3c2 stin[n] q3c1 stin[n] q3c0 stin[n] q2c2 stin[n] q2c1 stin[n] q2c0 stin[n] q1c2 stin[n] q1c1 stin[n] q1c0 stin[n] q0c2 stin[n] q0c1 stin[n] q0c0 stin[n]q1c 2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1? stin[n]q0c2-0 operation 0xx normal operation 100 lsb of each channel is replaced by ?0? 101 lsb of each channel is replaced by ?1? 110 msb of each channel is replaced by ?0? 111 msb of each channel is replaced by ?1?
zl50018 data sheet 97 zarlink semiconductor inc. bit name description 15 - 12 unused reserved. in normal functional mode, these bits must be set to zero. 11 - 9 stohz[n]a2 - 0 (valid only for stio0-15) stohz additional advancement bits : 8 - 7 sto[n]fa1 - 0 output stream[n] fractio nal advancement bits: 6 - 4 sto[n]ad2 - 0 output stream[n] bit adva ncement selection bits: the binary value of these bits refers to the number of bits that the output stream is to be advanced relative to fpo. the maximum value is 7. zero means no advancement. 3 - 0 sto[n]dr3 - 0 output data rate selection bits: note: [n] denotes output stream from 0 - 31. table 63 - stream output control register 0 - 31 (socr0 - 31) bits external read/write address: 0200 h - 021f h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 stohz [n]a2 stohz [n]a1 stohz [n]a0 sto[n] fa1 sto[n] fa0 sto[n] ad2 sto[n] ad1 sto[n] ad0 sto[n] dr3 sto[n] dr2 sto[n] dr1 sto[n] dr0 stohz[n]a2-0 additional advancement (2.048 mbps, 4.096 mbps, 8.192 mbps) additional advancement (16.384 mbps) 000 0 bit 0 bit 001 1/4 bit 2/4 bit 010 2/4 bit 4/4 bit 011 3/4 bit reserved 100 4/4 bit 101-111 reserved sto[n]fa1-0 advancement (2.048 mbps, 4.096 mbps, 8.192 mbps streams) advancement (16.384 mbps streams) 00 0 0 01 1/4 bit 2/4 10 2/4 bit reserved 11 3/4 bit stin[n]dr3 - 0 data rate 0000 disabled: stio hiz (stohz driven high) 0001 2.048 mbps 0010 4.096 mbps 0011 8.192 mbps 0100 16.384 mbps 0101 - 1111 reserved
zl50018 data sheet 98 zarlink semiconductor inc. bit name description 15 - 8 unused reserved. in normal functional mode, these bits must be set to zero. 7 - 0 st[n] brs7 - 0 stream[n] ber receive start bits: the binary value of these bits refers to the input channel in which the ber data starts to be compared. note: [n] denotes input stream from 0 - 31 table 64 - ber receiver start register [n] (brsr[n]) bits bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8 - 0 st[n] bl8 - 0 stream[n] ber length bits: the binary value of these bits refers to the number of consecutive channels expected to receive the ber pattern. the maximum number of ber channels is 32, 64, 128 and 256 for the data rates of 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps respectively. the minimum number of ber channels is 1. if these bits are set to zero, no ber test will be performed. note: [n] denotes input stream from 0 - 31 table 65 - ber receiver length register [n] (brlr[n]) bits external read/write address: 0300 h - 031f h reset value: 0000 h 1514131211109876543210 00000000st[n] brs7 st[n] brs6 st[n] brs5 st[n] brs4 st[n] brs3 st[n] brs2 st[n] brs1 st[n] brs0 external read/write address: 0320 h - 033f h reset value: 0000 h 1514131211109876543210 0000000st[n] bl8 st[n] bl7 st[n] bl6 st[n] bl5 st[n] bl4 st[n] bl3 st[n] bl2 st[n] bl1 st[n] bl0
zl50018 data sheet 99 zarlink semiconductor inc. bit name description 15 - 2 unused reserved. in normal functional mode, these bits must be set to zero. 1st[n] cber stream[n] bit error rate counter clear: when this bit is high, it resets the internal bit error counter and the stream ber receiver error register to zero. 0st[n] sber stream[n] bit error rate test start: when this bit is high, it enables the ber receiver; starts the bit error rate test. the bit error test result is kept in the ber receiver error (brer[n]) regi ster. upon the completion of the ber test, set this bit to zero. note that the rbereb bit must be set in the ims register first. note: [n] denotes input stream from 0 - 31 table 66 - ber receiver control register [n] (brcr[n]) bits bit name description 15 - 0 st[n] bc15 - 0 stream[n] ber count bits (read only): the binary value of these bits refers to the bit error counts. when it reaches its maximu m value of 0xffff, t he value will be held and will not rollover. note: [n] denotes input stream from 0 - 31 table 67 - ber receiver error register [n] (brer[n]) bits - read only external read/write address: 0340 h - 035f h reset value: 0000 h 15141312111098765432 1 0 00000000000000st[n] cber st[n] sber external read address: 0360 h - 037f h reset value: 0000 h 1514131211109876543210 st[n] bc15 st[n] bc14 st[n] bc13 st[n] bc12 st[n] bc11 st[n] bc10 st[n] bc9 st[n] bc8 st[n] bc7 st[n] bc6 st[n] bc5 st[n] bc4 st[n] bc3 st[n] bc2 st[n] bc1 st[n] bc0
zl50018 data sheet 100 zarlink semiconductor inc. 24.0 memory 24.1 memory address mappings when a13 is high, the data or connection memory can be accessed by the microprocessor port. bit 1 - 0 in the control register determine the access to th e data or connection memory (cm_l or cm_h). msb (note 1) stream address (st0 - 31) channel address (ch0 - 255) a13 a12a11a10 a9 a8 stream [n] a7a6a5a4a3a2a1a0 channel [n] 1 1 1 1 1 1 1 1 1 . . . . . 1 1 . . . . . . 1 1 0 0 0 0 0 0 0 0 0 . . . . . 0 0 . . . . . . 1 1 0 0 0 0 0 0 0 0 1 . . . . . 1 1 . . . . . . 1 1 0 0 0 0 1 1 1 1 0 . . . . . 1 1 . . . . . . 1 1 0 0 1 1 0 0 1 1 0 . . . . . 1 1 . . . . . . 1 1 0 1 0 1 0 1 0 1 0 . . . . . 0 1 . . . . . . 0 1 stream 0 stream 1 stream 2 stream 3 stream 4 stream 5 stream 6 stream 7 stream 8 . . . . . stream 14 stream 15 . . . . . . stream 30 stream 31 0 0 . . 0 0 0 0 . . 0 0 . . . . 0 0 . . . . 1 1 0 0 . . 0 0 0 0 . . 0 0 . . . . 1 1 . . . . 1 1 0 0 . . 0 0 1 1 . . 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 . 1 1 . . . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 1 1 . . . . 1 1 . . . . 1 1 0 1 . . 0 1 0 1 . . 0 1 . . . . 0 1 . . . . 0 1 ch 0 ch 1 . . ch 30 ch 31 (note 2) ch 32 ch 33 . . ch 62 ch 63 (note 3) . . . . ch126 ch 127 (note 4) . . . . ch 254 ch 255 (note 5) note 1: a13 must be high for access to data and connection memory positions. a13 must be low to access internal registers. note 2: channels 0 to 31 are used when serial stream is at 2.048 mbps. note 3: channels 0 to 63 are used when serial stream is at 4.096 mbps. note 4: channels 0 to 127 are used when serial stream is at 8.192 mbps. note 5: channels 0 to 255 are used when serial stream is at 16.384 mbps. table 68 - address map for memory locations (a13 = 1)
zl50018 data sheet 101 zarlink semiconductor inc. 24.2 connection memory low (cm_l) bit assignment when the cmm bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. the connection memory low bit assi gnment for the channel transmission mode is shown in table 69 on page 101. bit name description 15 uaen conversion between -law and a-law enable when this bit is low, normal switch without -law/a-law conversion. connec- tion memory high will be ignored. when this bit is high, switch with -law/a-law conversion, and connection memory high controls the conversion method. 14 v/c variable/constant delay control when this bit is low, the output data for this channel will be taken from con- stant delay memory. when this bit is set to high, the output data for this channel will be taken from variable delay memory. note that varen must be set in control register first. 13 - 9 ssa4 - 0 source stream address the binary value of these 5 bits re presents the input stream number. 8 - 1 sca7 - 0 source channel address the binary value of these 8 bits re presents the input channel number. 0 cmm = 0 connection memory mode = 0 if this is low, the connection memory is in the normal switching mode. bit13 - 1 are the source stream number and channel number. note: for proper - law/a-law conversion, the cm_h bits should be set before bit 15 (uaen bit) is set to high. table 69 - connection memory low (cm_l) bit assignment when cmm = 0 151413121110987654321 0 ua en v/c ssa 4 ssa 3 ssa 2 ssa 1 ssa 0 sca 7 sca 6 sca 5 sca 4 sca 3 sca 2 sca 1 sca 0 cmm =0
zl50018 data sheet 102 zarlink semiconductor inc. when cmm is one, the device is programmed to perform one of the special per-channel transmission modes. bits pcc0 and pcc1 from connection memory are used to select the per-channel tristate, message or ber test mode as shown in table 70 on page 102. 24.3 connection memory high (cm_h) bit assignment connection memory high provides the detailed information required for -law and a-law conversion. icl and ocl bits describe the input coding law and the output coding law, respectively. they are used to select the expected pcm coding laws for the connection, on the tdm inputs, and on the tdm outputs. the v /d bit is used to select the class of coding law. if the v /d bit is cleared (to select a voice connection), the icl and ocl bits select between a-law and -law specifications related to g.711 voice coding. if the v /d bit is set (to select a data connection), the icl and ocl bits select between various bit inverting protoc ols. these coding laws are illustrated in the following table. if the icl is different than the ocl, all data bytes passing through the switch on th at particular connection are translated between the indicated laws. if the icl and the oc l are the same, no coding law translation is performed. bit name description 15 uaen conversion between -law and a-law enable (message mode only) when this bit is low, message mode has no -law/a-law conversion. connec- tion memory high will be ignored. when this bit is high, message mode has -law/a-law conversion, and con- nection memory high controls the conversion method. 14 - 11 unused reserved. in normal functional mode, these bits must be set to zero. 10 - 3 msg7 - 0 message data bits: 8-bit data for the message mode. not used in the per-channel tristate and ber test modes. 2 - 1 pcc1 - 0 per-channel control bits: these two bits control the corresponding entry?s value on the stio stream . 0 cmm = 1 connection memory mode = 1. if this is high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel mes- sage mode or per-channel ber mode. note: for proper - law/a-law conversion, the cm_h bits should be set before bit 15 (uaen bit) is set to high. table 70 - connection memory low (cm_l) bit assignment when cmm = 1 151413121110987654321 0 ua en 0000msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 pcc 1 pcc 0 cmm =1 pc c1 pc c0 channel output mode 0 0 per channel tristate 0 1 message mode 10 ber test mode 11 reserved
zl50018 data sheet 103 zarlink semiconductor inc. the icl, the ocl bits and v /d bit only have an effect on pcm code tran slations for constant delay connections, variable delay connections and per-channel message mode. bit name description 15 - 5 unused reserved. in normal functional mode, these bits must be set to zero. 4v /d voice/data control when this bit is low, the corresponding channel is for voice. when this bit is high, the corresponding channel is for data. 3 - 2 icl1 - 0 input coding law 1 - 0 ocl1 - 0 output coding law note 1: for proper - law/a-law conversion, the cm_h bits should be set before bit 15 of cm_l is set to high. note 2: refer to g.711 standard for detail information of different laws. table 71 - connection memory high (cm_h) bit assignment 151413121110987654321 0 00000000000v /d icl 1 icl 0 ocl 1 ocl 0 icl1- 0 input coding law for voice (v /d bit = 0) for data (v /d bit = 1) 00 ccitt.itu a-law no code 01 ccitt.itu -law abi 10 a-law w/o abi inverted abi 11 -law w/o magnitude inversion all bits inverted ocl1 -0 output coding law for voice (v /d bit = 0) for data (v /d bit = 1) 00 ccitt.itu a-law no code 01 ccitt.itu -law abi 10 a-law w/o abi inverted abi 11 -law w/o magnitude inversion all bits inverted
zl50018 data sheet 104 zarlink semiconductor inc. 25.0 applications this section contains application-sp ecific details for clock and crystal operation and power supply decoupling. 25.1 osci master clock requirement the device requires a 20 mhz master clock source at the osci pin when operating in master mode or in divided slave with osc mode. the clo ck source may be either an ex ternal clock oscillator connecte d to the osci pin, or an external crystal connected between the osci and osco pins. if an external clock source is present, osc_en must be tied high. note that using a crystal is only suitabl e for wider tolerance applications (i.e. 100 ppm). stratum 4e applications (i.e. 32 ppm) should use a clock oscillator while stratum 3 applications (i.e. 4.6 ppm) should use a temperature-compensated clock module. see application note zlan-68 for a list of oscillators and crystals that can be used with zarlink pll?s and digital switches with embedded pll?s. 25.1.1 external crystal oscillator when an external crystal osci llator is used, a complete osc illator circuit made up of a crys tal, resistor and capacitors is shown in figure 23 on page 104. xc is a buffered vers ion of the 20 mhz input clock connected to the internal circuitry. figure 23 - crystal oscillator circuit the accuracy of a crystal o scillator circuit depends on th e crystal tolerance as well as the load capacitance tolerance. typically, for a 20 mhz crystal specified wi th a 32 pf load capacitance, each 1 pf change in load capacitance contributes approximately 9 ppm to the fr equency deviation. consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. the trimmer capacitor shown in figure 23 on page 104 may be used to compensate for capacitive effects. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional fi lter components and is less likely to generate spurious responses. the crystal accuracy only affects the output clock accuracy in the free run or the holdover mode. the crystal specification is as follows: frequency 20 mhz tolerance as required oscillation mode fundamental resonance mode parallel osco 25 pf 1 m ? 25 pf 20 mhz osci xc 2 k dx
zl50018 data sheet 105 zarlink semiconductor inc. 25.1.2 external clock oscillator when an external clock o scillator is used, numerous parameters mu st be considered. t hey include absolute frequency, frequency change over temperature, output ri se and fall times, output levels and duty cycle. the output clock should be connected directly (not ac coupled) to the os ci input of the device, and the osco output should be left open as shown in figure 24 on page 105. xc is a buffered version of the 20 mhz input clock connected to the internal circuitry. figure 24 - clock oscillator circuit for applications requiring 32ppm clock accuracy, the following requirements should be met: for applications requiring stratum 3 compliance ( 4.6 ppm clock accuracy), the following temperature compensated clock oscillato r module may be used. load capacitance 20 pf - 32 pf maximum series resistance 35 ? approximate drive level 1 mw frequency 20.000 mhz to l e r a n c e 32 ppm rise and fall time 10 ns duty cycle 40% to 60% frequency 20.000 mhz to l e r a n c e 4.6 ppm rise and fall time 10 ns duty cycle 40% to 60% +3.3 v 20 mhz out gnd 0.1 uf +3.3 v osco osci no connection xc 2k dx
zl50018 data sheet 106 zarlink semiconductor inc. 26.0 dc parameters * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). absolute maximum ratings* parameter symbol min. max. units 1 i/o supply voltage v dd_io -0.5 5.0 v 2 core supply voltage v dd_core -0.5 2.5 v 3 input voltage v i_3v -0.5 v dd + 0.5 v 4 input voltage (5 v-tolerant inputs) v i_5v -0.5 7.0 v 5 continuous current at digital outputs i o 15 ma 6 package power dissipation p d 1.5 w 7 storage temperature t s - 55 +125 c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated . characteristics sym. min. typ. ? max. units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_io 3.0 3.3 3.6 v 3 positive supply v dd_core 1.71 1.8 1.89 v 4 input voltage v i 03.3v dd_io v 5 input voltage on 5v-tolerant inputs v i_5v 05.05.5v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current - v dd_core i dd_core 165 ma 2 supply current - v dd_io i dd_io 75 ma c l = 30 pf 3 input high voltage v ih 2.0 v 4 input low voltage v il 0.8 v 5 input leakage (input pins) input leakage (bi-di rectional pins) i il i bl 5 5 a a 0 zl50018 data sheet 107 zarlink semiconductor inc. 27.0 ac parameters ? characteristics are over recommended operating conditions unless otherwise stated. figure 25 - timing parameter measurement voltage levels ac electrical characteristics ? - timing parameter measurement voltage levels characteristics sym. level units conditions 1 cmos threshold v ct 0.5 v dd_io v 2 rise/fall threshold voltage high v hm 0.7 v dd_io v 3 rise/fall threshold voltage low v lm 0.3 v dd_io v timing reference points all signals v hm v ct v lm
zl50018 data sheet 108 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 26 - motorola non-multiplexed bus timing - read access ac electrical characteristics ? - motorola non-multiplexed bus mode - read access characteristics sym min. typ. max. units test conditions 2 1cs de-asserted time t csd 15 ns 2ds de-asserted time t dsd 15 ns 3cs setup to ds falling t css 0 ns 4r/w setup to ds falling t rws 10 ns 5 address setup to ds falling t as 5 ns 6cs hold after ds rising t csh 0 ns 7r/w hold after ds rising t rwh 0 ns 8 address hold after ds rising t ah 0 ns 9 data setup to dta low t ds 8 ns c l =50pf 10 data hold after ds rising t dh 7 ns c l =50pf, r l =1 k (note 1) 11 acknowledgement delay time. from ds low to dta low: registers memory t akd 75 185 ns ns c l =50pf c l =50pf 12 acknowledgement hold time. from ds high to dta high t akh 412nsc l =50pf, r l =1k (note 1) 13 dta drive high to hiz t akz ns note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 17.2 on page 48) must be applied before the first microprocessor access is performed after the reset pin is set high. ds a0-a13 d0-d15 t csh t ah t rws r/w t as t rwh t akd t ds t akh dta v ct v ct v ct v ct v ct v ct valid address valid read data t css t dsd cs t akz t csd t dh
zl50018 data sheet 109 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 27 - motorola non-multiplexed bus timing - write access ac electrical characteristics ? - motorola non-multiplexed bus mode - write access characteristics sym. min. typ . max. units test conditions 2 14 cs de-asserted time t csd 15 ns 15 ds de-asserted time t dsd 15 ns 16 cs setup to ds falling t css 0 ns 17 r/w setup to ds falling t rws 10 ns 18 address setup to ds falling t as 5 ns 19 data setup to ds falling t ds 0 ns c l =50pf 20 cs hold after ds rising t csh 0 ns 21 r/w hold after ds rising t rwh 0 ns 22 address hold after ds rising t ah 0 ns 23 data hold from ds rising t dh 5 ns c l =50pf, r l =1k (note 1) 24 acknowledgement delay time. from ds low to dta low: registers memory t akd 55 150 ns ns c l =50pf c l =50pf 25 acknowledgement hold time. from ds high to dta high t akh 412nsc l =50pf, r l =1k (note 1) 26 dta drive high to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s (see section 17.2 on page 48) must be applied before the first microprocessor access is performed after the reset pin is set high. ds a0-a13 t csh t ah t rws r/w t as t rwh t akd t akh dta v ct v ct v ct v ct v ct t css t dsd cs t akz d0-d15 t dh t ds v ct valid write data t csd valid address
zl50018 data sheet 110 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 28 - intel non-multiplexed bus timing - read access ac electrical characteristics ? - intel non-multiplexed bus mode - read access characteristics sym. min. typ . max. units test conditions 2 27 cs de-asserted time t csd 15 ns 28 rd setup to cs falling t rs 10 ns 29 wr setup to cs falling t ws 10 ns 30 address setup to cs falling t as 5 ns 31 rd hold after cs rising t rh 0 ns 32 wr hold after cs rising t wh 0 ns 33 address hold after cs rising t ah 0 ns 34 data setup to rdy high t ds 8 ns c l =50pf 35 data hold after cs rising t dh 7 ns c l =50pf, r l =1k (note 1) 36 acknowledgement delay time. from cs low to rdy high: registers memory t akd 175 185 ns ns c l =50pf c l =50pf 37 acknowledgement hold time. from cs high to rdy low t akh 412nsc l =50pf, r l =1k (note 1) 38 rdy drive low to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 17.2 on page 48) must be applied before the first microprocessor access is performed after the reset pin is set high. cs a0-a13 d0-d15 t ah t ws wr t wh t akd t ds t akh rdy v ct v ct v ct v ct v ct valid address valid read data t csd t akz t rs rd t rh v ct t as t dh
zl50018 data sheet 111 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 29 - intel non-multiple xed bus timing - write access ac electrical characteristics ? - intel non-multiplexed bus mode - write access characteristics sym. min. typ . max. units test conditions 2 39 cs de-asserted time t csd 15 ns 40 wr setup to cs falling t ws 10 ns 41 rd setup to cs falling t rs 10 ns 42 address setup to cs falling t as 5 ns 43 data setup to cs falling t ds 0 ns c l =50pf 44 wr hold after cs rising t wh 0 ns 45 rd hold after cs rising t rh 0 ns 46 address hold after cs rising t ah 10 ns 47 data hold after cs rising t dh 5 ns c l =50pf, r l =1k (note 1) 48 acknowledgement delay time. from cs low to rdy high: registers memory t akd 55 150 ns ns c l =50pf c l =50pf 49 acknowledgement hold time. from cs high to rdy low t akh 412nsc l =50pf, r l =1k (note 1) 50 rdy drive low to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (section 17.2 on page 48) must be applied before the first microprocessor access is performed after the reset pin is set high. cs a0-a13 d0-d15 t ah t rs rd t rh t akd t akh rdy v ct v ct v ct v ct v ct valid address t csd t akz t ws wr t wh v ct t as valid write data t ds t dh
zl50018 data sheet 112 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 30 - jtag test port timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? see ?performance characteristics notes? on page 133. ac electrical characteristics ? - jtag test port timing characteristic sym. min. typ. max. units notes 1 tck clock period t tckp 100 ns 2 tck clock pulse width high t tckh 20 ns 3 tck clock pulse width low t tckl 20 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 60 ns 8 tdo output delay t tdod 30 ns c l =30pf 9trst pulse width t trstw 200 ns ac electrical characteristics ? - osci 20 mhz input timing characteristic sym. min. typ. max. units notes? 1 input frequency accuracy -4.6 4.6 ppm 1 2 duty cycle 40 60 % 3 input rise or fall time t ir, t if 3ns17 t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst
zl50018 data sheet 113 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 00 (16.384 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 40 61 115 ns 2 fpi input frame pulse setup time t fpis 20 ns 3 fpi input frame pulse hold time t fpih 20 ns 4 cki input clock period t ckip 55 61 67 ns 5 cki input clock high time t ckih 27 34 ns 6 cki input clock low time t ckil 27 34 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 01 (8.192 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 90 122 220 ns 2 fpi input frame pulse setup time t fpis 45 ns 3 fpi input frame pulse hold time t fpih 45 ns 4 cki input clock period t ckip 110 122 135 ns 5 cki input clock high time t ckih 55 69 ns 6 cki input clock low time t ckil 55 69 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 10 (4.096 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 90 244 420 ns 2 fpi input frame pulse setup time t fpis 110 ns 3 fpi input frame pulse hold time t fpih 110 ns 4 cki input clock period t ckip 220 244 270 ns 5 cki input clock high time t ckih 110 135 ns 6 cki input clock low time t ckil 110 135 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns
zl50018 data sheet 114 zarlink semiconductor inc. figure 31 - frame pulse input and clock input timing diagram (st-bus) figure 32 - frame pulse input and clock input timing diagram (gci-bus) t fpiw fpi t fpih t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki t fpiw fpi t fpih t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki
zl50018 data sheet 115 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 33 - st-bus input timing diagram when operated at 2 mbps, 4 mbps, 8 mbps ac electrical characteristics ? - st-bus/gci-bus input timing characteristic sym. min. typ. max. units test conditions 1 sti setup time 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t sis2 t sis4 t sis8 t sis16 5 5 5 8 ns ns ns ns 2sti hold time 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t sih2 t sih4 t sih8 t sih16 8 8 8 8 ns ns ns ns v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit7 ch0 bit6 ch0 t sis4 t sih4 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit0 ch63 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit1 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 sti0 - 31 sti0 - 31 sti0 - 31 v ct v ct bit0 ch31 v ct input frame boundary bit0 ch127
zl50018 data sheet 116 zarlink semiconductor inc. figure 34 - st-bus input timing diagram when operated at 16 mbps figure 35 - gci-bus input timing diagram wh en operated at 2 mbps, 4 mbps, 8 mbps v tt cki fpi (16.384 mhz) bit0 ch255 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit1 ch255 16.384 mbps t sis16 t sih16 input frame boundary sti0 - 31 v ct bit7 ch0 v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit0 ch0 bit1 ch0 t sis4 t sih4 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 sti0 - 31 sti0 - 31 sti0 - 31 v ct v ct bit7 ch31 v ct input frame boundary bit7 ch127
zl50018 data sheet 117 zarlink semiconductor inc. figure 36 - gci-bus input timing diagram when operated at 16 mbps v tt cki fpi (16.384 mhz) bit7 ch255 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch255 16.384 mbps t sis16 t sih16 input frame boundary sti0 - 31 v ct bit0 ch0
zl50018 data sheet 118 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ac electrical ch aracteristics ? - st-bus/gci-bus multiplied slave mode output timing ? characteristics are over recommended operating conditions unless otherwise stated. ac electrical ch aracteristics ? - st-bus/gci-bus divided slave mode output timing ? characteristics are over recommended operating conditions unless otherwise stated. ac electrical characteristics ? - st-bus/gci-bus master mode output timing characteristic sym. min. typ. max. units test conditions 1 stio delay - active to active at 2.048 mbps at 4.096 mbps at 8.192 mbps at 16.384 mbps t sod2 t sod4 t sod8 t sod16 1 1 1 1 8 8 8 8 ns ns ns ns c l = 30pf characteristic sym. min. typ. max. units test conditions 1 stio delay - active to active at 2.048 mbps at 4.096 mbps at 8.192 mbps at 16.384 mbps t sod2 t sod4 t sod8 t sod16 0 0 0 0 6 6 6 6 ns ns ns ns c l = 30pf characteristic sym. min. typ. max. units test conditions 1 stio delay - active to active at 2.048 mbps at 4.096 mbps at 8.192 mbps at 16.384 mbps t sod2 t sod4 t sod8 t sod16 -6 -6 -6 -6 0 0 0 0 ns ns ns ns c l = 30pf
zl50018 data sheet 119 zarlink semiconductor inc. figure 37 - st-bus output timing diagra m when operated at 2, 4, 8 or 16 mbps figure 38 - gci-bus output timing diagra m when operated at 2, 4, 8 or 16 mbps bit0 ch255 cko0 fpo0 (4.096 mhz) 8.192 mbps 4.096 mbps 2.048 mbps output frame boundary stio0 - 31 stio0 - 31 stio0 - 31 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit0 ch63 bit7 ch0 bit6 ch0 bit0 ch31 t sod2 t sod4 t sod8 v ct v ct v ct bit0 ch127 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch255 bit1 ch255 bit2 ch0 bit1 ch0 bit0 ch0 bit7 ch1 bit6 ch1 bit5 ch1 bit4 ch1 bit3 ch1 bit2 ch1 bit1 ch1 v ct t sod16 16.384 mbps stio0 - 31 cko0 fpo0 (4.096 mhz) output frame boundary bit7 ch255 8.192 mbps 4.096 mbps 2.048 mbps stio0 - 31 stio0 - 31 stio0 - 31 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit7 ch31 t sod2 t sod4 t sod8 v ct v ct v ct bit7 ch127 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch255 bit6 ch255 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch1 bit1 ch1 bit2 ch1 bit3 ch1 bit4 ch1 bit5 ch1 bit6 ch1 v ct t sod16 16.384 mbps stio0 - 31
zl50018 data sheet 120 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. * test condition is r l = 1 k, c l = 30 pf; high impedance is measured by pulling to the app ropriate rail with r l , with timing corrected to cancel the time taken to discharge c l . figure 39 - serial output and external control figure 40 - output drive enable (ode) ac electrical characteristics ? - st-bus/gci-bus output tristate timing characteristic sym. min. typ. max. units test conditions * 1 stio delay - active to high-z t dz -2 -3 -8 8 7 0 ns ns ns master mode multiplied slave mode divided slave mode 2 stio delay - high-z to active t zd -2 -3 -8 8 7 0 ns ns ns master mode multiplied slave mode divided slave mode 3 output drive enable (ode) delay - high-z to active cki @ 4.096 mhz cki @ 8.192 mhz cki @ 16.384 mhz t zd_ode 77 260 138 77 ns ns ns ns master or multiplied slave mode divided slave mode 4 output drive enable (ode) delay - active to high-z cki @ 4.096 mhz cki @ 8.192 mhz cki @ 16.384 mhz t dz_ode 77 260 138 77 ns ns ns master or multiplied slave mode divided slave mode t dz stio t zd stio cko0 v ct v ct tristate valid data v ct tristate valid data fpo0 v ct hiz hiz stio ode t zd_ode valid data t dz_ode v ct v ct
zl50018 data sheet 121 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. figure 41 - input and out put frame boundary offset ac electrical characteristics ? - slave mode input/output frame boundary alignment characteristic sym. min. typ. max. units notes 1 input and output frame offset in divided slave with cki mode t fbos 513ns 2 input and output frame offset in multiplied slave t fbos 2 10 ns input reference jitter is equal to zero. cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) input frame boundary cko0 fpo0 (4.096 mhz) output frame boundary t fbos
zl50018 data sheet 122 zarlink semiconductor inc. figure 42 - fpo0 and cko0 or fpo3 and cko3 (4.096 mhz) timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpo0 and cko0 or fpo3 and cko3 (4.096 mhz) timing (master mode, divided slave mode, or multiplied slave mode with less than 10 ns of jitter on cki ) characteristic sym. min. typ. ? max. units notes 1 fpo0 output pulse width t fpw0 239 244 249 ns c l = 30 pf 2 fpo0 output delay from the fpo0 falling edge to the output frame boundary t fodf0 117 127 ns 3 fpo0 output delay from the output frame boundary to the fpo0 rising edge t fodr0 117 127 ns 4 cko0 output clock period t ckp0 239 244 249 ns c l = 30 pf 5 cko0 output high time t ckh0 117 127 ns 6 cko0 output low time t ckl0 117 127 ns 7 cko0 output rise/fall time t rck0 , t fck0 5ns ac electrical characteristics ? - fpo0 and cko0 or fpo3 and cko3 (4.096 mhz) timing (multiplied slave mode with more than 10 ns of jitter on cki) characteristic sym. min. typ. ? max. units notes 1 fpo0 output pulse width t fpw0 218 244 270 ns c l = 30 pf 2 fpo0 output delay from the fpo0 falling edge to the output frame boundary t fodf0 117 127 ns 3 fpo0 output delay from the output frame boundary to the fpo0 rising edge t fodr0 97 146 ns 4 cko0 output clock period t ckp0 218 244 270 ns c l = 30 pf 5 cko0 output high time t ckh0 117 127 ns 6 cko0 output low time t ckl0 97 146 ns 7 cko0 output rise/fall time t rck0 , t fck0 5ns t fpw0 t fodr0 t fodf0 fpo0 cko0 t ckl0 t ckh0 t ckp0 t rck0 t fck0 output frame boundary v ct v ct
zl50018 data sheet 123 zarlink semiconductor inc. figure 43 - fpo1 and cko1 or fpo3 and cko3 (8.192 mhz) timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpo1 and cko1 or fpo3 and cko3 (8.192 mhz) timing (master mode, divided slave mode, or multiplied slave mode with less than 10 ns of jitter on cki) characteristic sym. min. typ. ? max. units notes 1 fpo1 output pulse width t fpw1 117 122 127 ns c l = 30 pf 2 fpo1 output delay from the fpo1 falling edge to the output frame boundary t fodf1 56 66 ns 3 fpo1 output delay from the output frame boundary to the fpo1 rising edge t fodr1 56 66 ns 4 cko1 output clock period t ckp1 117 122 127 ns c l = 30 pf 5 cko1 output high time t ckh1 56 66 ns 6 cko1 output low time t ckl1 56 66 ns 7 cko1 output rise/fall time t rck1 , t fck1 5ns ac electrical characteristics ? - fpo1 and cko1 or fpo3 and cko3 (8.192 mhz) timing (multiplied slave mode with more than 10 ns of jitter on cki) characteristic sym. min. typ. ? max. units notes 1 fpo1 output pulse width t fpw1 106 122 127 ns c l = 30 pf 2 fpo1 output delay from the fpo1 falling edge to the output frame boundary t fodf1 56 66 ns 3 fpo1 output delay from the output frame boundary to the fpo1 rising edge t fodr1 46 66 ns 4 cko1 output clock period t ckp1 106 122 148 ns c l = 30 pf 5 cko1 output high time t ckh1 46 87 ns 6 cko1 output low time t ckl1 46 87 ns 7 cko1 output rise/fall time t rck1 , t fck1 5ns t fpw1 t fodr1 t fodf1 fpo1/fpo3 cko1/cko3 t ckl1 t ckh1 t ckp1 t rck1 t fck1 output frame boundary v ct v ct
zl50018 data sheet 124 zarlink semiconductor inc. figure 44 - fpo2 and cko2 or fpo3 and cko3 (16.384 mhz) timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical ch aracteristics ? - fpo2 and cko2 or fpo3 and cko3 (16.384 mhz) timing (master mode, divided slave mode, or multiplied slave mode with less than 10 ns of jitter on cki) characteristic sym. min. typ. ? max. units notes 1 fpo2 output pulse width t fpw2 56 61 66 ns c l = 30 pf 2 fpo2 output delay from the fpo2 falling edge to the output frame boundary t fodf2 25 36 ns 3 fpo2 output delay from the output frame boundary to the fpo2 rising edge t fodr2 25 36 ns 4 cko2 output clock period t ckp2 56 61 66 ns c l = 30 pf 5 cko2 output high time t ckh2 25 36 ns 6 cko2 output low time t ckl2 25 36 ns 7 cko2 output rise/fall time t rck2 , t fck2 5ns ac electrical characteristics ? - fpo2 and cko2 or fpo3 and cko3 (16.384 mhz) timing (multiplied slave mode with more than 10 ns of jitter on cki) characteristic sym. min. typ. ? max. units notes 1 fpo2 output pulse width t fpw2 56 61 66 ns c l = 30 pf 2 fpo2 output delay from the fpo2 falling edge to the output frame boundary t fodf2 25 36 ns 3 fpo2 output delay from the output frame boundary to the fpo2 rising edge t fodr2 25 36 ns 4 cko2 output clock period t ckp2 47 61 76 ns c l = 30 pf 5 cko2 output high time t ckh2 17 43 ns 6 cko2 output low time t ckl2 17 43 ns 7 cko2 output rise/fall time t rck2 , t fck2 5ns t fpw2 t fodr2 t fodf2 fpo2/fpo3 cko2/cko3 t ckl2 t ckh2 t ckp2 t rck2 t fck2 output frame boundary v ct v ct
zl50018 data sheet 125 zarlink semiconductor inc. figure 45 - fpo3 and cko3 (32.768 mhz) timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac electrical characteristics ? - fpo3 and cko3 (32.768 mhz) timing (master mode, divided slave mode, or multiplied slave mode with less than 10 ns of jitter on cki) characteristic sym. min. typ. ? max. units notes 1 fpo3 output pulse width t fpw3 27 30.5 34 ns c l = 30 pf 2 fpo3 output delay from the fpo3 falling edge to the output frame boundary t fodf3 10 18 ns 3 fpo3 output delay from the output frame boundary to the fpo3 rising edge t fodr3 10 21 ns 4 cko3 output clock period t ckp3 27 30.5 34 ns c l = 30 pf 5 cko3 output high time t ckh3 12 19 ns 6 cko3 output low time t ckl3 12 19 ns 7 cko3 output rise/fall time t rck3 , t fck3 5ns ac electrical characteristics ? - fpo3 and cko3 (32.768 mhz) timing (multiplied slave mode with more than 10 ns of jitter on cki characteristic sym. min. typ. ? max. units notes 1 fpo3 output pulse width t fpw3 27 30.5 34 ns c l = 30 pf 2 fpo3 output delay from the fpo3 falling edge to the output frame boundary t fodf3 12 19 ns 3 fpo3 output delay from the output frame boundary to the fpo3 rising edge t fodr3 12 19 ns 4 cko3 output clock period t ckp3 17 30.5 44 ns c l = 30 pf 5 cko3 output high time t ckh3 532ns 6 cko3 output low time t ckl3 12 18 ns 7 cko3 output rise/fall time t rck3 , t fck3 5ns t fpw3 t fodr3 t fodf3 fpo3 cko3 t ckl3 t ckh3 t ckp3 t rck3 t fck3 output frame boundary v ct v ct
zl50018 data sheet 126 zarlink semiconductor inc. figure 46 - fpo4 and cko4 timing diagram (1.544/2.048 mhz) ? characteristics are over recommended operating conditions unless otherwise stated. ? characteristics are over recommended operating conditions unless otherwise stated. ac electrical characteristics ? - cko4 (1.544 mhz) timing (only when dpll is active) characteristic sym. min. typ. max. units notes 1 cko4 output clock period t ckp4 645 650 ns c l =30pf 2 cko4 output high time t ckh4 320 327 ns 3 cko4 output low time t ckl4 320 327 ns 4 cko4 output rise/fall time t rck4 , t fck4 5ns ac electrical characteristics ? - cko4 (2.048 mhz) timing (only when dpll is active) characteristic sym. min. typ. max. units notes 1 cko4 output clock period t ckp4 485 492 ns c l =30pf 2 cko4 output high time t ckh4 241 247 ns 3 cko4 output low time t ckl4 241 247 ns 4 cko4 output rise/fall time t rck4 , t fck4 5ns fpo0 cko4 t ckl4 t ckh4 t ckp4 t rck4 t fck4 output frame boundary v ct v ct
zl50018 data sheet 127 zarlink semiconductor inc. figure 47 - cko5 timing diagram ? characteristics are over recommended operating conditions unless otherwise stated. ac electrical characteristics ? - cko5 (19.44 mhz) timing (only when dpll is active) characteristic sym. min. typ. max. units notes 1 fpo5 output pulse width t fpw5 49 55 ns c l = 30pf 2 fpo5 output delay from the fpo5 falling edge to the output frame boundary t fodf5 22 28 ns 3 fpo5 output delay from the output frame boundary to the fpo5 rising edge t fodr5 21 32 ns 4 cko5 output clock period t ckp5 50 53 ns 5 cko5 output high time t ckh5 23 27 ns 6 cko5 output low time t ckl5 24 28 ns 7 cko5 output rise/fall time t rck5 , t fck5 5ns t fpw5 t fodr5 t fodf5 fpo5 cko5 t ckh5 t ckp5 t rck5 t fck5 output frame boundary v ct v ct (shares output pin with fpo_off2) t ckl5
zl50018 data sheet 128 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? see ?performance characteristics notes? on page 133 figure 48 - ref0 - 3 reference input/output timing ac electrical ch aracteristics ? - ref0-3 reference input to cko output timing characteristic sym. min. max. units notes ? 1 minimum input pulse width high or low t rpmin 16 ns 1,2,3,16 2 input rise or fall time t ir,(or t if) 5ns 3 input to cko0 output delay (no input jitter) with reference 8 k, 2 m, 4 m, 8 m and 16 mhz 1.544 mhz 19.44 mhz t rd -7 6 -10 0 15 -2 ns fpo[n] cko[n] v ct ref0-3 t rd v ct v ct t ir t rpmin
zl50018 data sheet 129 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? see ?performance characteristics notes? on page 133 ? characteristics are over recommended operating conditions unless otherwise stated. ? see ?performance characteristics notes? on page 133 ? characteristics are over recommended operating conditions unless otherwise stated. ? see ?performance characteristics notes? on page 133 ac electrical characteristics ? - master mode output timing characteristic sym. min. max. units notes ? 1 cko0 to cko1 (8.192 mhz) delay t c1d -1 2 ns 1-5,16 2 cko0 to cko2 (16.384 mhz) delay t c2d -1 3 ns 3 cko0tocko3 (32.768 mhz/16.384 mhz/8.192 mhz/4.096 mhz) delay t c3d -4 0 ns 4 cko0 to cko4 delay 2.048 mhz 1.544 mhz t c4d -2 -12 3 7 ns 5 cko0 to cko5 (19.44 mhz) delay t c5d 612ns ac electrical characteristics ? - divided slave mode output timing characteristic sym. min. max. units notes ? 1 cko0 to cko1 (8.192 mhz) delay t c1d -1 2 ns 1-5,16 2 cko0 to cko2 (16.384 mhz) delay t c2d -1 3 ns 3 cko0tocko3 (32.768 mhz/16.384 mhz/8.192 mhz/4.096 mhz) delay t c3d -2 2 ns ac electrical characteristics ? - multiplied slave mode output timing characteristic sym. min. max. units notes ? 1 cko0 to cko1 (8.192 mhz) delay t c1d -1 2 ns 1-5,16 2 cko0 to cko2 (16.384 mhz) delay t c2d -1 3 ns 3 cko0tocko3 (32.768 mhz/16.384 mhz/8.192 mhz/4.096 mhz) delay t c3d -1 3 ns
zl50018 data sheet 130 zarlink semiconductor inc. figure 49 - output timing (st-bus format) fpo0 cko1 cko0 v ct cko2 cko3 cko4 cko5 v ct v ct v ct v ct v ct v ct t c1d t c2d t c5d t c3d (1.544 mhz) (4.096 mhz) (8.192 mhz) (16.384 mhz) (32.768 mhz) (19.44 mhz) t c4d
zl50018 data sheet 131 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? see ?performance characteristics notes? on page 133 dpll performance characteristics ? - accuracy & switching characteristics min. max. units conditions/notes ? 1 freerun mode accuracy -0.003 0 ppm 1,5,7 2 initial holdover frequency stability -0.03 0.03 ppm 1,4,8 3 pull-in/hold-in range (stratum 3) -20 20 ppm 1,3,7,9 4 reference far hysteresis limit (stratum 3) -11.4 11.4 ppm 1,3,7,9,15 5 reference near hysteresis limit (stratum 3) -9.8 9.8 ppm 6 output phase continuity for reference switch 1 1. reference switching to normal, holdover, or freerun mode 31 ns 15 7 normal output phase alignment speed (phase slope) 56 s/s 10 8 normal phase lock time 2 2. -4.6 to +4.6 ppm locking 60 s 1,3,7,9,10,12 9 fast phase lock time 1 s 1,3,7,9,10,11,12
zl50018 data sheet 132 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * see ?performance characteristics notes? on page 133. dpll performance characteristics ? - output jitter generation (unfiltered except for cko5) characteristics typ. ? units conditions/notes * 1 jitter at cko0 and cko3 (4.096 mhz) 810 ps-pp 1-6,16 2 jitter at cko1 and cko3 (8.192 mhz) 800 ps-pp 3 jitter at cko2 and cko3 (16.384 mhz) 710 ps-pp 4 jitter at cko3 (4.096, 8.192, 16.384, or 32.768 mhz) 670 ps-pp 5 jitter at cko4 (1.544 mhz or 2.048 mhz) 1.544 mhz 2.048 mhz 1060 630 ps-pp ps-pp 6 jitter at cko5 (19.44 mhz) unfiltered jitter 500 hz - 1.3 mhz jitter 65 khz - 1.3 mhz jitter 12 khz - 1.3 mhz jitter 770 540 460 510 ps-pp ps-pp ps-pp ps-pp
zl50018 data sheet 133 zarlink semiconductor inc. performance characteristics notes ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd_core at 1. 8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. 1. jitter on master clock input (xin) is 100 ps pp or less. 2. jitter on reference input (ref0-3) is 2 ns pp or less. 3. normal mode selected. 4. holdover mode selected. 5. freerun mode selected. 6. jitter is measured without an output filter. 7. accuracy of master clock input (xin) is 0 ppm. 8. accuracy of master clock input (xin) is 100 ppm. 9. capture range is programmed to +/-20 ppm; inaccuracy of xin shifts this range. 10. phase alignment speed (phase slope) is programmed to 7 ns/125 s. 11. fast lock is enabled. 12. low pass filter is programmed to 1.9 hz. 13. applies to all programmable low pass filter selections of 1.9 hz and above. 14. any input reference switch or state switch (e.g.; ref0 to ref3, normal to holdover, etc.). 15. auto-holdover is programmed to 9.913 ppm & 11.287 ppm. 16. 30 pf load on output pin.
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes b 214440 1 26june03
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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